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TPS3106: Rise and Fall Times

Jeffrey Frye1
Prodigy 10 points
Part Number: TPS3106

I'm planning on using the TPS3106 for a reset circuit for an FPGA and need to know the output rise/fall times for the output Reset Sense and Reset VDD pins. The FPGA has a requirement on the input that the reset signal needs to have rise/fall times of less than 1us. I'm pulling these reset outputs from the voltage supervisor high with a 10k-Ohm resistor. It didn't seem like there was any specification in the timing diagrams in the datasheet on this.

Thanks

  • 0
    TI__Mastermind 19580 points

    Hi Jeffrey,

    The TPS3106 is an open drain device. We do not specify the rise and fall times of the device as they vary with the pull up resistor/ pull up voltage/ output capacitance. From my experience, the rise/fall times are much less than a 1us. You will have to test this out in your system for proper functionality but I see no issue with the timing requirement.