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UCC28C42: Reference Stability

Adam Berg
Prodigy 50 points
Part Number: UCC28C42

This a question concerning the stability of the UCC28C4 controller when a bypass capacitor below 0.1uF is used on the reference pin. Here is some background information: the most recent datasheet says that 0.1uF is the minimum value in order to ensure the accuracy of the voltage reference. In addition, going below this value is said to allow excessive noise, inadequate phase margin, and negatively impact rejection ratio. We are aware that each of these can be issues, but in this case, we are only concerned with those parameters that have a noticeable affect on stability.

Knowing the above information, can you explain under what conditions the stability of the circuit could be compromised when using a bypass capacitor under 0.1uF? And furthermore, if a 0.047uF capacitor were to be used, to what extent would an instability impact operation of the circuit (phase margin of the loop, etc.).

If you require further explanation to fully answer the questions, please let me know.

This question is a followup of case number: CS0140853

  • 0
    TI__Genius 13660 points

    Hi Adam,

    VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC, a minimum capacitor 0.1uF at REF pin is requested to keep the voltage stability, a capacitor under 0.1 uF may not large enough to supply its load. Basically phase margin and negatively impact rejection ratio you mentioned are not concerned here.

    Regards,

    Teng

  • 0 in reply to Teng Feng
    Prodigy 50 points

    Hello Teng,

    You mentioned that phase margin and rejection ratio are not concerns here, and that 0.1uF may not support the load.

    This being the case, what is the maximum load that a 0.047uF capacitor can support for this application?

    Thank you,

    Adam

  • 0 in reply to Teng Feng
    Prodigy 50 points

    Hello Teng,

    I am not sure if you saw my previous message or not, but we are still curious about the phrase that you used - "supply its load". For our application, we estimate the load would be around 5mA, which is far below the maximum. Would a 0.047uF bypass capacitor on VREF be sufficient for this load case?

    For some context, the circuit in which this part is used was designed 19 years ago. The datasheet from 2001 states that a 0.1uF capacitor should be used, but the most recent datasheet states that it this value is required. As such, a value lower than 0.1uF was chosen. We simply want to know if the value of this bypass capacitor is acceptable for our application.

    Thank you for working with us,

    Adam

  • 0 in reply to Adam Berg
    TI__Mastermind 34465 points

    Adam,

    A minimum of 0.1uF is required on VREF.
    The capacitor should be a high quality ceramic (X7R or X5R dielectric) . If its surface mount it should be in a minimum case size of 0805.
    The reason for this is that there is usually a lot of switching noise spikes within the power supply and you need to ensure that the reference voltage and also 
    VCC bias supply to the pwm controller are adequately filtered from this noise. The data sheet probably got changed because some users were using no capacitor at all.
    There is no reason to use a value lower than 0.1uF and doing so risks making your power supply become susceptible to noise pickup.I recommend that for new product build you change to 0.1uF and if there is no issue with your older product you should not have to rework the parts
    Its insurance for a better quality product and it doesn't cost anything extra to change from .047uF to 0.1uF

    Regards

    John

  • 0 in reply to John Griffin1
    Prodigy 50 points

    I was told that I should post a reply here with a new question until this post is closed.

    On the datasheet for this chip, there is a graph that shows the maximum duty cycle as a function of frequency. However, it only lists this information for two capacitor values on the RTCT pin. I would expect that for higher capacitance, say 2.2nF, the curve would be shifted lift and have a steeper downward slope. Could you please tell me what the expected maximum duty cycle would be for a capacitor value of 2.2nF and operating frequency around 215kHz? I'm looking for an answer based purely on the datasheet.

  • 0 in reply to Adam Berg
    TI__Genius 13660 points

    Hi Adam,

    please kindly understand the section 8.3.5 Reduced-Discharge Current Variation in the datasheet.
    The minimum dead time can be approximately calculated by：

    Tdmim= CT * (3 V- 0.7 V)    /    (    8.4 mA   -    ( 5V-   (3V+0.7V)/2) / RT          )

    Of course, you can use a simulation to see the change of maximum duty cycle intuitively.

    Regards,

    Teng