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TPS65916: Power-down sequence requirements

Nicholas Carley
Genius 9925 points
Part Number: TPS65916
Other Parts Discussed in Thread: AM5716

I’ve been struggling with meeting the power-down sequence requirements in the TPS65916 data sheet, SLVSD09C, pg 75. The figure there describes it well:


The intent is clear – just need to initiate the “ACTIVE to OFF” sequence a few milliseconds before VCC falls below ~2.8V. Creating the PGOOD signal is simple, but what to use for the PMIC “ENABLE” pin is the mystery. Presumably, one of the “OFF Requests” from table 5-3 would work, but I’ve eliminated them one-by-one for various reasons:

  • PWRON pin: requires long assertion to cause OFF requeset (‘long press key’ = 4s minimum).
  • PWRDOWN: not available, using GPIO_0 as REGEN1.
  • RESET_IN: not available, using GPIO_1 as NRESWARM.
  • VSYS_LO: Artificially pull VCCA low just enough to trigger OFF request, but not cause instant shutdown? Is this possible?
  • POWERHOLD: Planning to use this for Power-On Acknowledge per section 5.3.5.
  • GPADC_SHUTDOWN: Requires SW to set up OFF request trigger from adc input. (remaining four OFF Requests are not HW accessible)

Am I overlooking something? Is there a recommended way of triggering the power-down sequence with no (or minimal) SW setup?
By the way, our product will have no power switch, and no power-off or standby function. If it’s plugged in, it runs.

Thanks,
Nick

  • 0
    TI__Mastermind 30310 points

    Nick,

    I have assigned this to the experts on the team, but you may not receive a response until tomorrow as I assigned the post after 4pm here in Dallas.

  • 0
    TI__Mastermind 28260 points

    Hello,

    Open Drain PGOOD signal can be ORed with RESET_IN. Is there any issue with that?

    Regards

  • 0 in reply to Mahmoud Harmouch
    TI__Genius 9925 points

    Hi Mahmoud,

    My understanding is, there is no RESET_IN function on the TPS65916 unless the processor re-programs GPIO_1 for that function. That would eliminate NRESWARM, which is the OTP function on GPIO_1. NRESWARM is driven by processor RSTOUTN in the application examples and is described in the errata as workaround for some reset-related issues.

    The concern is:

    If we do change GPIO_1 to RESET_IN and drive it from the OR of PGOOD and RSTOUTN, then we effectively exchange warm reset (without power cycle) for cold reset with full power cycle. We could probably live with that, but it looks to me like it would only work if the AM5716 allows its RSTOUTN to be pulled high after its power supplies are cycled off. Otherwise, there’s a reset deadlock with PMIC and proc each resetting the other. This doesn’t happen using NRESWARM because that function is triggered by falling edge rather than low level. Maybe could be solved with a one-shot reset generator chip following the processor’s reset output.

    Having the processor initialize the PMIC in order to get a clean power-down does present risks with initial board turn-on, code load, development and troubleshooting. Even on a working system, there’s a window of vulnerability between power-on sequence completion and processor boot to the point of PMIC configuration.

    What are your thoughts/alternative options?

    Thanks,
    Nick

  • 0 in reply to Nicholas Carley
    TI__Mastermind 28260 points

    Hello Nick, I'm thinking about 2 options:

    1- Connect VCC supply to voltage supervisor and output controls POWERHOLD

    2- Connect VCC supply to voltage supervisor. Output is AND gated with your system power on signal. The AND gate output controls the POWERHOLD

    Does this work for your system?

    Regards

  • 0 in reply to Mahmoud Harmouch
    TI__Mastermind 28260 points

    Hello,

    This thread is considered resolved. Please create another thread or send message offline for further concern.

    Regards