TPS65910: What are the power-on and power-off timing characteristics of the AM335x?

Please refer to TPS65910Ax User's Guide for AM335x Processors (Rev. F), Table 2. EEPROM Configuration for TPS65910Ax on page 5 and also refer to the TPS65910 datasheet. For newer devices, the Register Map definitions are released as a Technical Reference Manual (TRM) for unique programming variant of the device and all variants share a single datasheet. The User's Guide/Datasheet relationship is similar for TPS65910.

Figure 3 in the User's Guide is a visual representation of the order listed in Table 2. In Table 2, each output rail (LDO or DCDC) has a row called "time slot" with an integer value in the Option Selected column.

From the TPS65910 datasheet, each delay between time slots is referred to as tdsONx, where tdsON1 is the delay between time slot 0 (power-on event) and time slot 1, tdsON2 is the delay between time slot 1 and time slot 2, and so on. The delays are specified as tdsON1 = 66 × tCK32k = 2.06 ms, tdsON2-8 = 64us × tCK32k = 2 ms.

• CORRECT: When you use TPS65910AA1, TPS65910A3A1, and TPS65910A31A1 devices and set BOOT1=VRTC (1 - High), BOOT0=GND (0 - Low), the PMIC will power-up automatically with the correct settings for Sitara AM335x using a EEPROM register map.
• INCORRECT: If you use BOOT1 = 0, BOOT0 = 0 or BOOT1 = 0, BOOT0 = 1, all versions of the PMIC will load a register map from an OTP bank and will NOT be correct for Sitara AM335x. Instead, these PMICs will match the settings outlined in section 5.22 of the datasheet.

Taishi,

Yes, your understanding is correct.

The time in between "sequence slots" is controlled by the TSLOT_LENGTH field, bits 5..4 in DEVCTRL2_REG register (address 0x40).

TSLOT_LENGTH  = Time slot duration programming (EEPROM bit): Default 0x3 (11b = 2ms)

00b : 0 µs

01b : 200 µs

10b : 500 µs

11b : 2 ms

Taishi,

Taishi Ando said:

1.If TSLOT_LENGTH is 2 ms, what are the Max and Min values?

1. Internal 32-kHz RC oscillator: CK32K_CTRL = 1b --> Min = 2ms*(1-0.15) = 1.7ms, Max = 2ms*(1+0.15) = 2.3ms (at room temp, 25°C)
2. Bypass Clock: CK32K_CTRL = 0b, clock connected from OSC32KIN to OSC32KOUT --> 2ms +/-__%
   • The accuracy of the 2ms delay is determined by the accuracy of the external clock source

3. Crystal oscillator: CK32K_CTRL = 0b, OSC32KIN: input, OSC32KOUT floating --> 2ms +/- __ %
   • The accuracy of the 2ms delay is determined by the accuracy of the crystal oscillator

Taishi Ando said:

2.What is the slew rate for each power supply?

In the TPS65910 datasheet, refer to "t on, off to on" specification for the following outputs: VIO SMPS, VDD1 SMPS, and VDD2 SMPS (350 µs), 

Refer to the "turn-on time" specification for the following outputs: VRTC LDO (2.2 ms) , VDD3 SMPS (200 µs),  VDIG1/2, VAUX33, VMMC, VAUX1/2, VDAC, and VPLL LDOs (100 µs).

And refer to the TSTEP value in VDD1 and VDD2 registers (addresses 0x21, 0x24, and ), default = 7.5 mV/µs, for the slew rate for changes in output voltage during dynamic voltage scaling (DVS).

Taishi Ando said:

3.What are the rise conditions for each sequence?
   Time(TSLOT_LENGTH)? Voltage for previous sequence?

The sequencer is not dependent on the output voltage of the previous supply. I will use Figure 3 from TPS65910Ax User's Guide for AM335x Processors (Rev. F) as a reference

VDAC turns on at Time Slot #1, then VDIG1/2 turn on at Time Slot #2, and the tdSON2 time can be measured from when VDAC begins to turn on to when VDIG1/2 begin to turn on. This will be 2ms+/-__%, depending on which 32-kHz clock is used as a reference.

The time will not be tdson2 + turn-on time of VDAC.

Therefore, the time from when VDAC begins to turn on to when VDD2 begins to turn on will be (2ms +/-__%)*6 time slots = 12ms +/-__%