LM5114: size of "VDD cap?"

Brian,

Are you talking about just 100n+10n cap? That may be too small. Depending on the mosfet you are driving you should need >1uF total decoupling capacitance next to LM5114 for VDD.

You can estimate the minimum viable decoupling capacitance on the MOSFET gate charge, VGS, supply voltage (VDD), and and how much ripple/Delta(V) is acceptable. You might want extra pads in the PCB layout to  populate extra caps if you see fit.

In this case, a good reference design would is the LM5114 EVM. The schematic in Section 7 specifies 1uF capacitance for LM5114. I would take this as a minimum value. And be aware that X7R capacitance will be lower as VDD increases. So recommended to check the cap datasheet to see the effecitive capacitance at your design VDD level, and ensure voltage ratings for the X7R capacitor are sufficiently high.

The purpose of decoupling caps is to provide very local source of charge that can respond to quick changes in demand, such as charging MOSFET gate at MHz frequencies. Parasitic inductance, like PCB trace inductance and even the cap's parasitic inductances prevent quick change in current which is why the presence of decoupling cap is necessary, otherwise there will be noise/rippling in VDD.

Wider PCB traces + placing several decoupling caps in parallel, rather than only putting single, reduces this inductance as well, and it is just as important as enough VDD decoupling capacitance.

Let me know if you have any other questions. If this cleared everything up, please click the green button.

Best

Dimitri 

Brian, 

An easy way is to choose bypass on the order of 100x larger than the gate cap. An even easier way is to simply match the 1uF bypass as used in the Evaluation board design! You'll see how we essentially get this equation from the equations below. 

Brian Machesney said:

I'll only be driving about 1/3 of the gate capacitance, but at 50X the frequency called out in the LM5114 EVM app note. Should I simply scale the total decoupling capacitance up 50X for dV/dt and down 3X for gate capacitance

Not exactly that, but frequency and gate cap both affect the choice.Gate cap of the MOSFET you are driving is the biggest impact, as that takes the most current every clock cycle. I think you shouldn't bother too much with decimal points and getting exact values. This is more to estimate the minimum viable bypass capacitance.

Heres one way to estimate: I_DD is quiescent current in LM5114 datasheet, D*I_GSS is the Gate-> source leakage in the MOSFET datasheet. Vripple will be chosen by you, say you want no more than 1% ripple on VDD for example. 

Brian Machesney said:

I can't find any specs for the ESL of garden-variety uF-sized caps. Can you point me to a useful reference?

I can point you to some references. There may not always be ESL specs listed. But know that Ceramic caps themselves already have lower ESL compared with other technologies.

• Here is a very good resource about capacitor selection, but in general X7R like you mentioned at the appropriate voltage rating will be a good choice.
• Here is the reference PPTX 
• Section 3.1 in This Technote gives some insight on capacitor sizing calculations in a gate driver.

I hope this is helpful and answered your question. If i have answered your question, please click the green button. And definitely let us know if you have more questions.

Best

Dimitri