LM5170: MOSFET Switching Loss Calculation

Hi Marc,

Thanks for reaching out with your question and for considering the LM5170 in your design.

Equations 55 and 56 are the ideal equation to calculate the rise time and fall time of the switch node. These don't include the gate resistance. Qg is the total gate charge of the MOSFET. This simplifies the equation.

What is the switching frequency is the LM5170 running at in your application? What is the power dissipation that is being calculated? Typically in these high power application the conduction losses dominate the switching loses.

Let me know if you have any questions.

Thanks,

Garrett

Hello Garrett,

Thank you for the prompt reply. I have some follow-up questions.

I believe that the total gate charge Qg is dependent upon the voltage level to which the gate is charged. Using TI's CSD18540Q5B MOSFET as an example, the gate charge is listed as 21 nC for Vgs = 4.5V and 44 nC for Vgs = 10V. I understand that it takes more charge to raise the gate voltage to 10V rather than 4.5V.

However, the switching loss of the MOSFET itself (not counting the driver loss) is determined from the overlap of the nonzero portions of Vds and Id. Assuming the LM5170 is provided a bias voltage of 10V, I presume the LM5170 gate drivers would drive the MOSFET gate voltages to a 10V level (less, perhaps, the diode drop for the HS bootstrap diode). However, for the turn-on, shouldn't the drain-source voltage (Vds) collapse to zero well before Vgs rises to 10V? Specifically, it seems Vds should collapse to zero after the gate voltage rises to the threshold voltage and the Miller capacitance is charged, i.e., at the end of the Miller plateau? I believe the excess charge to get from the end of the Miller plateau to the Vgs = 10V level should not affect the rise time that is used for calculating switch turn-on losses. (?) This is shown pretty clearly in figure 5 from TI document slyt664 ("MOSFET power losses and how they affect power-supply efficiency" by George Lakkas, 2016), which is replicated below.

Using the above figure, the turn-on loss would be 0.5*Vds*Id*(t1+t2), where (t1+t2) presumably corresponds to trise from the LM5170 datasheet. However, (t1+t2) corresponds to the time interval required to the end of the Miller plateau, rather than the total charge provided to the gate. In the above figure, the charge relevant for this time interval would be Qgs2 and Qgd, rather than Qg(tot). This is why I would like confirmation of which MOSFET charge parameter I should be using when estimating switching losses.

To answer your questions, I am initially using fsw = 100 kHz as the default switching frequency (same as for the EVM). If the switching losses are manageable, I plan to increase the frequency, e.g., to 200 kHz or 400 kHz, so as to reduce the low-side output ripple and perhaps reduce the required low-side bulk capacitance.

Presuming Vhv = 48V, Vlv = 8V, Irms = 30.8A, fsw = 100 kHz, and MOSFET = TI CSD18540Q5B:

d = 8V/48V = 0.167

Rdson(T=150 C & Vgs=10V) = 3.2 mOhm

Qc(tot@10V) = 41 nC

From this, I calculate the following power losses for the high-side (control) MOSFET in a buck mode:

Pcond = (0.167) * (30.8 A)^2 * (3.2 mOhm) = 0.5 W

t_rise = 41 nC/(4A) = 10.25 nsec

t_fall = 41 nC/(5A) = 8.2 nsec

Pswitch = 0.5*(48V)*(~30A)*(10.25 ns+8.2 nsec)*(100 kHz) = 1.32 W (Ipeak & Ivalley approximated as 30A each)

So, the switching losses make up a significant portion of the power that must be dissipated by the HS MOSFET, but I don't trust that the rise and fall times are properly estimated. (That is why I posed the previous questions.)

Having said that, the LS MOSFET (acting as a sync rect in buck mode) carries the bulk of the conducted loss in buck mode, since it is on for 83% of the time. If my assumptions are correct, the LS MOSFET in boost mode represents the worst-case power dissipation for my scenario, as it incurs significant conducted and switching losses. I want to have a reasonable understanding and approximation of these losses before I finalize my MOSFET choice.

Thanks again!

Marc

Marc,

The calculations in the slty664 are more accurate then the ones in the LM5170 datasheet. The datasheet equations are provided to give a quick estimation of the switching losses so that suitable MOSFETs can be found for the application. Rise and fall times are complicated to calculate as board parasitics can have a large impact as well. To be good first estimation is that the rise time and fall time will be in the 5ns~10ns range. This will help estimate the switching losses.

Your assumptions and calculations are correct. The low-side MOSFET is going to have the largest conduction losses while the high-side MOSFET is going to have the most switching losses. Selecting different MOSFETs for each leg is important to optimize the efficiency. It is okay to select a different MOSFET for the high-side and the low-side.

Let me know if you have any questions.

Thanks,

Garrett