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LMG1020: Input DC Characteristics is obscure

XiaoTao Ng
Intellectual 420 points
Part Number: LMG1020

Hi,Team:

  When I read the datasheet of LMG1020, I find that the Input DC Characteristics is obscure.

  Why the threshold of VIL and VIH  for IN+ & IN- vary so widely ?

  

 Tthe pulse width of output will be influenced when the threshold varies among different chip ,I think.

 Which distribution of the threshold of VIL and VIH  for IN+ & IN- follow ? or the  threshold will vary with temperature from the  perspective of  a sigle chip?

 The description for  the threshold of VIL and VIH  for IN+ & IN- is hard to catch. We hope more detailed descriptions will be provided since we care so much to control output pulse width definitely.

  • 0
    TI__Genius 12990 points

    Hi XiaoTao,

    Thanks for reaching out on lmg1020.

    The input threshold max/min differs by about 1V to satisfy the input hysteresis of 1V max. The input hysteresis is needed for the inputs to be stable with some ground bounce from high di/dt seen by common source inductance. The effect the ground bounce has on the input pin voltage depends on the inductance from the driver ground pin to the FET source. This is highlighted in equation 1 of section 8.2.2.1 in the lmg1020 datasheet. Section 8.2.2.2 also highlights how to achieve a 1ns pulse by using another 1020 to drive the input.

    The pulse with variation due to input threshold should not vary too much relative to the intrinsic driver distortion or PWD (positive pulse distortion as it's called in the datasheet) as long as the edges that the input sees are sharp. Or <1-10ns rise/fall on the input. A input buffer like SN74xx can also be used to help with fast input edges for this.

    Please let me know if this helps answer your question or you have any other questions.

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Intellectual 420 points

    Hi, Jeffery:

       Thank you for your professional guide. 

       According to datasheet, input level for IN+ /  IN- must  higher than 2.6V to ensure proper HIGH LOGIC

      It is pity that my FPGA IO is 1.8V LVCMOS specification which can offer 24mA driver capabilty. My design is more demanding for 

      PCB area since there are many channels . It is hard to add a level shifter or buffer chip to drive LMG1020 IN+/IN-  as showed in Figure 10.

      Maybe RC delay solution to acheive delay version showed in Figure 10 is the final solution for me.

      Thanks again.

       

     

       

  • 0 in reply to XiaoTao Ng
    TI__Genius 12990 points

    Hi XiaoTao,

    Thanks for the update,

    1020 needs a 3V swing on the input to switch properly so 1.8V will not be enough. You will either need a level shifter or buffer that accepts 1.8V as logic high to achieve this. Let me know if you have any other questions.

    Thanks,