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UC3843: uc3843 controller

Honorio GOUVEIA
Prodigy 30 points
Part Number: UC3843

Hello, 

I'm studying how to design a soft start for UC3843 and i'm a litlle confused about the soft tart time.

I saw when the VFB voltage reach 2.5V and ten the Voutput reach the disire target point and Vcomp deacrease  crossing Vss and the PNP goes Off, and after Vcomp increase until 2.5V( depend on the Vout) and stay stable.

  When the VFB voltage reach 2.5V the Voutput reach the disire targe point. What happen with Vcomp ? in this times VFB = Vref = 2.5V , what whappen with erro amplifier ???  and Vcomp =  ?? 

Sorry for my english.

BR

HG

  • 0
    TI__Genius 13660 points

    Hi HG,

    The Vcome is the output of the amplifier, it depends on the internal 2.5V reference, VFB pin voltage and the open loop gain of amplifier (AVOL). According the datasheet, AVOL is 60~90 dB when comp is 2~4V.   The duty cycle of PWM depends on the Vcomp and Isense pin.

    When output voltage reaches the target voltage, VFB is around 2.5V as design, which means at this time Vcomp reaches the value that keeps duty cycle and Vout operating as expected, then stay stable because of close loop control.

    You can design the soft start by using below circuit.

    Regards,

    Teng

  • 0 in reply to Teng Feng
    Prodigy 30 points

    Thanks Teng, 

    When output voltage reaches the target voltage, VFB is around 2.5V as design, which means at this time Vcomp reaches the value that keeps duty cycle and Vout operating as expected, then stay stable because of close loop control.

    in the figure 22  : The transistor is an emitter follower ? because it seems like Vcomp during the tss is 0V because the transistor pull down the Vcomp to ground.

    if the transitor work in emiter follower can explain me pls ?

    Is possible to determinate theoritical  the Vcomp value when, Vcomp reaches that keeps duty cycle and Vout operating as expected ? 

    Vcomp = 3*Rshunt*Ipeak + (1.4V) : expected operation, is it good ? 

    if know Ipeak  : tss = -Rss*Css*ln(1- ( Vcomp/(vref+Rss*Ib))): do you think is a good way to calcule the ss time ? 

    BR,

    HG

  • 0 in reply to Honorio GOUVEIA
    TI__Genius 13660 points

    Hi Honorio,

    1 & 4/. The operation of this soft start is very straightforward. The voltage on the Css capacitor starts at zero and begins to charge up to the value of VREF.
    Its time constant is Rss*Css. The voltage on the COMP pin is clamped by the forward voltage of the BE junction of the pnp transistor.

    VCOMP = VCss + 0.7. 

    This means that at startup VCOMP tracks the voltage on Css.    Forcing COMP to track the rising voltage on Css will ensure a soft start of the converter.
    You can make the assumption that the soft start time is Rss*Css.

    2./ Is possible to determinate theoretical  the Vcomp value when Vcomp reaches that keeps duty cycle and Vout operating as expected ? 

    The answer is Yes, the duty cycle and maximum primary current (Ipeak) can be calculated once output load is determined, then refer 3 to estimate Vcomp.

    3./ Vcomp = 3*Rshunt*Ipeak + (1.4V) : expected operation, is it good ? 

    Yes, it can be approximate estimated by this formula.

    Regards,

    Teng