LM74700-Q1: TVS diode selection for 12/24VDC operation

Hello Craig,

For 12V designs, recommendation is 33V rated bidirectional TVS. Maximum positive voltage is during the load dump which is 35V. So the load dump voltage will pass through the positve side TVS to the charge controller. No issues in 12V.

However, for 24V, suppressed load dump is 65V and SMBJ58A with a breakdown voltage of 64.4V min will pass the load dump voltage to charge controller.

65V is not good for LTC4020, so need to have some sort of over  voltage cut-off or over voltage clamp at the output to less the 60V. For over voltage cut-off or clamping the output, we need to use LM5060 after LM74700-Q1.

Let us know if the above suggestion works for you?

Regards,

Kari.

Thanks Kari,

Yes, you've accurately stated the problem I'm facing.  In this case, the board is very small and I've got very little real-estate left to implement another FET/IC combo, so the solution w/ the least components is most ideal in this case.  Do you have any other recommendations requiring fewer components?  Btw, during any over/under voltage conditions, the charge controller does not need to operate and probably shouldn't anyway.

I have a few other questions:

• FET is latched off subsequent to fault conditions and requires requiring EN, or UVLO to toggle.  This design is wired into the automotive system and there is no disconnect provision for Vin, i.e. no UVLO reset.  However, on page 18, it appears that restarting after OVP event is not a problem.  Can you clarify, especially in light of what is stated above wrt operation during under/over voltage and connecting timer to GND as mentioned below.
• Pg 3: LM5060 Vin spec is: 5.5V to 65V, operating, 75V disabled.  Does this mean if OVP is set at 55V, device is disabled above that and 75V input is therefore ok?
• Pg 3: LM5060 Vin min spec is stated as -25V, however SMBJ26A Vbr is 31.9Vmax.  Doesn't this violate the LM5060 input spec?
• Pg15:  Since there is no way to reset a fault condition, looks like connecting timer to GND is best option.  Not planning to use nPGD output.
• No UVLO requried, so tie to Vin.  Pg 17: @ 5.1V FET will be turned off.
• Pg19:  If no over-current sense required, is Rs still required?
• No reverse polarity protection required since this is in series w/ LM74700 on in-board side, correct?

Conclusion:  The LM5060 will be driving LTC4020 w/ Vin max = 60V, and NCV4264-2C w/ Vin =45V, so OVP would be set to ~40V.  Converter must supply up to 10A.  LM74700 ideal diode uses SIDR870ADP, so it seems that would be reasonable choice for this as well.  LM5060 circuit looks like OVP divider network, possibly Rs and Ro.

I can post the proposed design once these questions are answered.

Thanks!

One last thought...

Rather than using the LM74700 in series with the LM5060, what would your thoughts be using the LM5069-2 and replacing both w/ one IC and 2 back-to-back SIDR870ADP FET's?  Example here (PG2): https://www.ti.com/lit/an/snva683/snva683.pdf  Same functionality?  Thx,

Hi Craig,

I will let Rakesh comment on LM5060 design questions.

Apologies for the delay.

Regards,

Kari.

Hi Craig,

Can you please clarify on the below questions to proceed with LM5060 vs LM5069:

1. Do you need Automotive Grade / AEC Q-100 qualified device ?
2. Does your system need to meet all the automotive power line electrical transients (refer Figure 3 in http://www.ti.com/lit/ug/tiduc41/tiduc41.pdf )
3. Is a simple overvoltage protection device good enough ?
4. Please refer http://www.ti.com/tool/TIDA-01167 which covers Automotive 12V/24V Battery Input Protection 

Regards, Rakesh

Hi,

Thanks for your response.

The LM74700 Ideal diode circuit w/ associated TVS transient protection is already designed in and tested(LM74700 spec pg 18).  Rather than deleting this circuit and replacing w/ all-in-one using 5060 handling both FETS, my preference is to follow the existing circuit with over-voltage protection such as offered by the LM5060 (recommended previously).  My purpose for OVP is to protect the downstream LTC4020 and 5v regulator and cut off voltage at 37V.

I will not be testing to meet the full ISO specs for this design, but do need reverse polarity protection and basic transient protections.  This design does not need ride-thru, UVP or OCP as that can be provided by converter.  Fault or pwr good warnings are also not needed.  Primary concern is during turn-on and turn-off of FET's to stay within SOA.  It seems that w/ TVS diode SMBJ58A clamping at ~71Vmax and Vcutoff of 37V, FET will need Vds of ~34V at 7A during Ton/Toff.

Since 5060 latches during OVP, linear time of operation is limited, so Pd is also limited.

In LM5060 spec section 8.1.10, it says no reset is necessary after OVP event, however in app design, a reset circuit is shown.  Is this due to the other non-OVP faults?

Thx,  Craig