This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS53622: TPS53622

Part Number: TPS53622
Other Parts Discussed in Thread: TPS53679

Hello,

We want to design PVNN_AUX and P1V05_AUX of  Intel  Bakerville Skylake-D 85W SoC SKU with TPS53622.

But we don't sure if  the TPS53622 can support AVID when the PVNN_AUX voltage change.

The attchment is TPS53622 reference design,I want to know the AVID function is ok with AVID controls 2 MOSFETs in the reference design?

Or the method of AVID in the reference design had used in mass production?

Thank you!

TI_VR13_SkylakeD_Bakerville_Reference Design.pdf

  • Hi Wenxing,

    The AVID function is working fine by 2 FET's implementation. You can use that without issue.

    Thanks

    Chasel

  • Hello Chasel,

    Thank you very much!

    Now has a new question about TPS53622.

    In the referenc design, the SVID: 4 for PVNN,5 for P1V05, PMBUS=D0h, by ADDR TO VREF= 23.2K, ADDR TO GND= 21K.

    But I don't find the SVID address =5 in the menu of TPS53679_2P0_Design_Tool_Rev0_5?

    If the strap resistors can't set the svid address, it is done by PMBUS modify the MFR register?

    BTW, Can TI provide SCH review?

    Thank you!

  • Hi Wenxing,

    If the strap resistors can't set the svid address, it is done by PMBUS modify the MFR register?

    Yes, you are correct, to set SVID address by NVM.

    Please reach out your local sales support team for the SCH review, I believe you don't want to publish your schematic online... :)

    Thanks

    Chasel