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TPS65381A-Q1: About a Flag in the SPI frame

Juan Carlos Aguirre

Prodigy 80 points

Part Number: TPS65381A-Q1

Hi, I have a doubt with the meaning of a flag in the SPI first frame when I read the register SAFETY_CHECK_CTRL, after send a write command to that register

My question is:

The flag in the bit 3 (SPI WR access (during previous SPI frame-command phase)) is a warning about a non permitted write in the prev register or indicates that I just write the prev register?

over 5 years ago

0 Ivan Calzada over 5 years ago

TI__Expert 4690 points

Hi Juan Carlos,

STAT[3] will be set when your previous SPI transaction was a write command.

If you want to confirm you have sent a valid write or read command you can monitor STAT[0] bit.

STAT[0] bit will be set if any of the following SPI errors occurred during the previous SPI frame:

Truncated SPI frames
SPI transfers with more than 16 bits
SPI transfers with undefined commands
SPI transfers with incorrect command parity

Regards,
Ivan

0 Juan Carlos Aguirre over 5 years ago in reply to Ivan Calzada

Prodigy 80 points

Ok, thanks for solve my doubt