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TPS2596: Fault Indicator for Short Circuit Protection

Part Number: TPS2596

Hi team, 

I'd like to learn about the short-circuit behavior.

The fault indication from short-circuit event may depend on the ambient temperature and use conditions, but it may take several hundred milliseconds from shorting the output to stopping the output (FLT=L) by Overt Temperature Protection, doesn't it?

Does this mean that in some situations, the overheat protection may not work while in the current limit state (i.e., it may not cause the output to stop)?
If this is the case, does this mean that FLT cannot be monitored under the abnormal state?

Regards,

Itoh

  • HI Itoh,

    I am looking into this and will get back to you by end of today.

  • Hi Itoh,

    When a short circuit occurs, the current through the device increases very rapidly. As the current exceeds 1.5 x ILIM, the device engages a fast current clamping circuit to regulate down the current faster than the nominal overcurrent response time (tLIM). The device does not completely turn off the power FET to ensure uninterrupted power in the event of transient overcurrents or supply transients. As shown in figure 50 of the datasheet, the device starts limiting the current to a  foldback value ( value less than current limit setting). The output voltage drops in the current limiting state, resulting in increased power dissipation in the internal FET and might lead to thermal shutdown if the condition persists for an extended period of time.

    As you rightly said, the time taken for the device to reach Thermal Shutdown depends on various parameters like foldback current value, Short circuit impedance, input voltage, RthetaJA (Board Layout dependent), Ambient Temperature. The Power dissipation across the FET and RthetaJA are very important factors among them. Figure 26 and 27 in the datasheet shown the time taken for the device to reach thermal shutdown vs power dissipation across the FET for two different layouts.  

    For example, if the Vin = 3.3V and the current limit setting is low the power dissipation in the FET may not be high enough to increase the internal die temperature to Thermal Shutdown Threshold value. In this case, the FLT/ may not be asserted.

  • Hi Itoh,

    Hope your question is answered. Do you have any more questions ?

  • Praveen,

    I really appreciate your helpful answer.

    Now, my customer is checking our answer.

    I'd like to keep this thread open a couple of days to support additional question from my customer just in case.

    Regards,

    Itoh

  • Itoh,

    Sure, we will keep this thread open until customer gets his queries completely resolved.