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CSD97394Q4M: About VIA layout on recommended thermal pad

Part Number: CSD97394Q4M

Hi,

Could you tell me the recommended VIA layout dimensions on the thermal pad?



There was no description of the via size in the data sheet.
Customers want information similar to the following:



Regards,
Yusuke

  • Hi Yusuke,

    We don't have a PCB drawing with vias on datasheet for this part, but we do have recommendations for the GND vias on datasheet, please see below:

    Thanks!

    Best regards

    Bo Wang

  • Hi Yusuke,

    Sorry,  the picture that I attached to show the via recommendation is not shown in my previous reply, I don't know why this happened.

    Please check "9.3 Thermal Considerations" on datasheet for the via size recommendations.

    Thanks!

    Best regards

    Bo Wang

  • Hi Wang,

    Thank you for your support.
    I will contact the customer with the following:
    >Intentionally space out the vias from each other to avoid a cluster of holes in a given area. • Use the smallest drill size allowed in your design. The example in >Figure 17 uses vias with a 10 mil drill hole and a 16 mil capture pad. • Tent the opposite side of the via with solder-mask.

    However,
    If there is a layout example, there should be its dimensions and layout drawing.

    Could you provide the following layout design information?



    Regards,
    Yusuke

  • Hi Wang,

    Thank you for your kind support.
    Is there any update about Via layout information?

    Best regards,
    Yusuke

  • Hi Yusuke,

    This EVM is an old design, we used PADs for the design. We changed from PADs to Altium for PCB design several years ago and don't have the access to PADs anymore. I'm still checking to see if there is a way that I can get the information for you.

    Thanks!

    Best regards

    Bo

  • Hi Yusuke,

    We do have a .dxf for the via placement for CSD97394, but it seems that I cannot attach the file on e2e. Could you please request the file from TI sales.

    Thanks!

    Best regards

    Bo

  • Hi Bo,

    Thank you for your kind support.
    〉Could you please request the file from TI sales.

    I want to add TI sales and direct mail to you.
    Please give your address in a private message.
    Or can I send the file in a private message?

    Best regards
    Yusuke

  • Hi Yusuke,

    Please contact TI sales,  ask them to contact me and I'll send them the file.

    Thanks!

    Best regards

    Bo

  • Hi Bo,

    Thank you for your strong support.
    I received layout data from TIJ.
    I received an additional question about VIA information from customer.

    Is there an ideal aperture ratio for a metal mask opening relative to a pad?
    Or Is there a target value (xx%) for the bonding ratio between the thermal electrode and the pad on the board?

    Could you give me your advice?

    Best regards,
    Yusuke

  • Hi Yusuke,

     Please see below for the answers:

    (1) Is there an ideal aperture ratio for a metal mask opening relative to a pad?

    To maintain good bond line thickness of solder it is recommended to target at least 65% coverage. However we may need to look at the complexity of the pads as we will be dealing with different area and sizes. But as default 65% coverage is good for solder voiding and BLT

    (2) Or Is there a target value (xx%) for the bonding ratio between the thermal electrode and the pad on the board? 

     >50% of the area is OK, <50% will impact the electrical and thermals

     

    Thanks!

     

    Best regards

    Bo