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LMG3410R070: Half-Bridge design

Pranit Pawar
Intellectual 520 points
Part Number: LMG3410R070

Hi Experts,

I'm designing a BLDC motor driver, powered by 500V DC-bus. Using 600 GaN device leaves me with 100V VDS margin. So I've a very tight overshoot margin,  hence my layout should be really optimised.

I've decided an 80V maximum overshoot (can be less too). What I'm trying to do now is to get an approximate value of maximum permissible power loop inductance (Lp) for the given overshoot i.e. how high the power loop inductance can be such that the overshoot limit isn't exceeded. To find Lp, I know of one formula - V = Lp * di/dt.  I'm switching 10A current in 10ns (least), which gives me 1A/ns maximum slew rate 

I'm doing this theoretical exercise before making the layout because depending on the value of loop inductance I'll make further moves. If Lp is high, I'l buy leaded package (easy soldering), opt for 2 layer design, make a "relaxed" layout and get the work done quickly and cheaply. However, if Lp is low, I'll buy small packages, opt for 4 layer design and spend more time optimising the layout. Because time and money both are limited, I wish to make a wise decision up front. I don't want to continuously roll out iterations v1,v2,v3,.... till I get the desired overshoot.

My questions are - 
1. Is 1A/ns slew rate calculated correctly? (tf = tr =~10ns,   Imax = 10A)
2. How to calculate the loop inductance value Lp? Is L*di/dt method the correct way to "back calculate" the Lp value as stated?
3. What other factors, if any, have to taken into account for calculating the Lp value?

I don't need accurate answers but a close enough approximate to get started with the work. However, if there are any detailed resources available, I'll be glad to go through them.

Thanks!

  • 0
    TI__Genius 16390 points

    Hello Pranit,

    Thank you for reaching out to us!

    First, I want to remind you that the absolute maximum rating for our GaN is 480V. The 600V is there for overshoot/transient purposes. If you are trying to operate with 500V bus with our FET constantly, there can be chances of damaging the device. For this case, you can consider multilevel topologies.

    Here are my comments to your questions:

    1. Yes, this is a good estimation for turn-on. Normally for a half bridge application (say in buck configuration), the turn-off edge is soft-switched by utilizing the load current. Soft switching can significantly reduce the switching loss, and also the slew rate will be much slower.

    2. Yes, this is a good estimation. However, there are more inductance inside the GaN package etc. The actual power loop inductance allowed might be less.

    3. It's strongly suggested you make Lp as small as you can even if you have a large margin. Small Lp can make less switching loss, less stress on the device, less ringing and EMI problems, and overall better performance.

    Please let us know if you have any other questions!

    Regards,

  • 0 in reply to Yichi Zhang.
    Intellectual 520 points

    Hi Yichi, 

    Thanks for bringing that to attention, I've looked at other switches. The switch available locally here is quite big, but easy to solder and put heatsink on. However its Drain, Source lead inductances are ~1.5nH. So my min loop inductance is 3nH.

    Using L*di/dt, I did a Lp threshold calculation for 80V overshoot at 1A/ns commutation rate. That gives me Lp = 80nH. Lp is the overall loop inductance, pcb+switch leads+all other inductive parasitics.

    so now that I know 80nH is the maximum loop inductance I can have, then I'll opt for the locally available package and make efforts in optimising the layout. Does this sound good?

    I'm stressing on this pre-design estimate because time and money are scarce. Opting for the best solution and components is a bit costly for me. Using the locally available GaN switch relieves a lot of things but I doubtful whether 3nH inductance is allowable? If yes then with the layout and other parasitics, I plan on keeping Lp below 5nH

  • 0 in reply to Pranit Pawar
    TI__Genius 16390 points

    If you plan to go with the discrete GaN solution with different packaging, then you might encounter large gate loop and common source inductance as well. The performance of the system might be further negatively impacted.

    You can try discrete GaN+driver and try to optimize the power loop and gate loop. Based on the performance observed, you can decide if this solution is viable. If the cost is a big concern, I would say it is worth a try for you.

    Regards,

  • 0 in reply to Yichi Zhang.
    Intellectual 520 points

    I opted for non-integrated solution because of the flexibility and easy debugging it offers. There is Kelvin source pin on the package, so no worries about CSI. I willingly gave up few benefits of integrated package for flexibility. 

    would 5nH (max) loop inductance be viable for 1A/ns commutation? By the formula it'll give 5V overshoot. Even if practical effects are considered, Lp will be higher than estimated, but much below the safe limit. Any comments on recommended Lp value in my case and whether I should opt for leaded package (given that my di/dt = 1A/ns, VDC = 500V, VDS-max = 650V, VDS-ovshoot = 80v)

    Thanks!

  • 0 in reply to Pranit Pawar
    TI__Genius 16390 points

    From theoretical perspective, I don't see problems. You can try to optimize your layout to get the minimal loop inductance.

    Regards,