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TPS659039-Q1: TPS659039-Q1 Application Problem

user6309673
Prodigy 60 points
Part Number: TPS659039-Q1

Hi：

In our project，we found RESET_OUT pin has twice reset，as shown in the following figure. Please help to confirm whether this waveform is correct？and why the pin “RESET_OUT” has twice reset？

Thank you！

  • 0
    TI__Genius 10000 points

    Hi,

    Welcome to E2E! I cannot tell the time scale from this image, but this toggle could happen if you are doing a warm reset. Do you know if the NRESWARM pin was initiating a warm reset to the system?

    If this is the case, the RESET_OUT is set to complete a toggle during the warm reset to satisfy an errata listed for the Jacinto 6 processors. In the Jacinto 6 errata documentation, the processor requires a toggle on PORz to ensure that it doesn't get stuck (i862 in the errata documentation).

    Let me know if this warm reset may be what you are observing.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Prodigy 60 points

    Hi Nastasha：

    The waveform is as follows.(RED is RESET_OUT,BLUE is NRESWARM)

    And I disconnect the R56,RESET_OUT is the same as before.

  • 0 in reply to user6309673
    TI__Genius 10000 points

    Hi,

    Can you also try measuring LDOVRTC, POWERHOLD (GPIO_7), and RESET_IN?

    Also, do you know if the output rails (SMPS and LDOs) are staying high during this time?

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Prodigy 60 points

    Hi:

    The waveform is as follows.

    And the output rails (SMPS and LDOs) are staying high during this time.

  • 0 in reply to user6309673
    TI__Genius 10000 points

    Hi,

    Does this only happen at startup? If so, how is VIO_IN powered? It looks like this toggle may be occurring while the OTP settings are loading. To prevent this, VIO_IN should be supplied after VCC1.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Prodigy 60 points

    Hi：

    Yes，this happens only at startup. In our application，VIO_IN is supplied after VCC1 as you say.  VIO_IN is enabled by SMPS9.

  • 0 in reply to user6309673
    TI__Genius 10000 points

    Hi,

    Okay, thanks this looks okay. Hmm, can you also verify POWERHOLD (GPIO_7) remains high during the RESET_OUT toggle? The scope shot you have of POWERHOLD with RESET_IN is too zoomed in to see whether it toggles at the point RESET_OUT does. Also, is PWRON doing anything during the RESET_OUT toggle, or only remains high?

    Is RESET_OUT connected to anything besides the PORz of the processor? It is a push-pull signal, so it shouldn't need any pull up resistors.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Prodigy 60 points

    Hi：

    Yes,POWERHOLD (GPIO_7) remains high during the RESET_OUT toggle.PWRON is float with nothing connection.

    RESET_OUT is connected to PORZ and RTC_ISO of the processor. And RESET_OUT doesn't have pull up resistors in our application.

  • 0 in reply to user6309673
    TI__Genius 10000 points

    Hi,

    I am really surprised if no other digital rails of the PMIC are changing during the RESET_OUT toggle. Have you checked if any interrupts are being set? Can you read the INTx_STATUS registers through I2C?

    Thanks,
    Nastasha