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TPS2660: Question about /FLT Output when TPS26600 V_IN is off

Jim Brinkhurst1
Mastermind 44680 points
Part Number: TPS2660

Hi 

My customer is using TPS26600 in a redundant power application with active ORing.

They have the following configuration and questions:

We’re using two TPS26600s in an ORing configuration similar to Figure 64 in the datasheet – here are some of our implementation specifics:

  • FLT pins are pulled up to the micro supply rail with 100k resistors, FLT pins go to their own micro pins
  • UVLO and OVP set to trip at 1.4V and 72.5V (essentially disabled)
  • Input voltages ~30V
  • Mode connected to ground with a 402k resistor per Table 2 to set current limit with latchoff
  • RTN tied to ground

We’ve noticed that when IN2 is unpowered but IN1 is powered and both are enabled, the FLT pin still asserts low on the TPS26600 powered from IN2. Upon taking a closer look, this appears to be corroborated by the Note on page 34

“ All control pins of the un-powered TPS2660x device in the Active ORing configuration will measure approximately 0.7 V drop with respect to GND. The system micro-controller should ignore IMON and FLT pin voltage measurements of this device when these signals are being monitored.”

 I understand that the fault signal is more so a “power good” than an actual fault indicator. However, the behavior of asserting a fault when there is no input power is undesired in our application. I have two questions

  1. How is the pull down FET on the FLT pin, which appears to be an N-type enhancement MOSFET from the block diagram in section 9.2, able to actually turn on when there is no input supply? Does the internal AVDD pull power from the output? My understanding of it being “open-drain” is that it would be unable to assert if the chip is unpowered.
  2. Is there any way we can configure the chip or the fault signal in order to bypass this behavior?

With some additional testing we see the following: It seems that when using the TPS26600 in an OR configuration, the fault flag will assert whenever the chip is not actively supplying current to the load (i.e. not forward biased). Is that true?

Thanks for your help.

Best regards,

Jim B

  • 0
    TI__Guru** 105361 points

    Hi Jim,

    Thanks for reaching out and the explanation.

    We have design trick tapping from the Vout node to keep the GATE of the pull down FET on the FLT pin to High. This voltage helps to turn-ON the pull down FET on the FLT pin to assert FLT pin LOW.

    With some additional testing we see the following: It seems that when using the TPS26600 in an OR configuration, the fault flag will assert whenever the chip is not actively supplying current to the load (i.e. not forward biased). Is that true?

    Correct. Any condition which disables the internal FET (SWEN=0) leads to asserting fault flag.

    Best Regards, Rakesh