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TPS65381A-Q1: At startup the TPS goes into safe state after making minor changes to the SPI with HALCoGen

Part Number: TPS65381A-Q1
Other Parts Discussed in Thread: HALCOGEN

We are experiencing problems with the communication between a Hercules RM48 and a  TPS65381A-Q1 when configuring the TPS65381A-Q1 after startup.
HALCoGen is used to configure SPI4. Our initial setting was:


With this configuration the communication works, but we do not meet the minimal value of t_hlcs 788 us as specified by SLVSDJ1A.
Therefore we changed the configuration to this:

We verified with a logic analyser that the SPI timing is still good, but the TPS65381A-Q1 seems to jump to safe state, instead of staying in diagnostic state during initialisation.

Do you have any suggestions what might be the cause of this behaviour, as I cannot see any relevant changes caused by the changed configuration?

  • Hi,

    Here are a few thing you might want to check to determine the reason TPS65381A-Q1 is jumping SAFE state. 

    1. The main reason the TPS65381A-Q1 will jump to SAFE state is due to a DIAGNOSTIC state time-out. I would suggest confirming that the time between NRES pin changing to high (device entering to DIAGNOSTIC state) to the moment the SPI command to set DIAG_EXIT_MASK bit is less than 512 ms.
    2. Double check SPI communication meets all SPI timing parameters in Figure 4-2 of the device datasheet (SLVSDJ1A). You probably already did this since you mentioned SPI timing is still good.
    3. When the device jumps to SAFE execute a RD_SAFETY_STAT_4 and decode the SPI error-status bits. 

    Please let me know if any of these suggestion helped.

    Regards,
    Ivan

  • Thank you Ivan, just for our understanding if we revert to the old configuration and the t_hlcs will be less then 788 us, what will be the consequence?
    Does this result in the second SPI frame not being processed by the companion chip, or can other side effects occur?

  • Hi,

    This delay is intended for SPI commands to be propagated to the TPS65381A-Q1 registers.The risk of not meeting this delay might be that if you execute a write operation and execute a read command with t_hlcs less than 788 ns, then the read data might not reflect that register content of the write operation.

    One thing I have noticed in your previous messages is that you specify t_hlcs in mciroseconds (788 us). However, this specification is in nanoseconds. I assume this is a typo but want to confirm this is not the actual configuration error. 

    Regards,
    Ivan

  • Hello Ivan

    Thank you, that makes things more clear for us.
    You are right, I mistakenly spoke about microseconds when I meant nanosecond, my apologies.

    Regards Jim