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About Cin and Cout Buck converter layout

Hello all,

I could find in the apps note and datasheet that input capacitor should be placed to the Vin closely. How long is the best length between Vin and Cin, how long is the maximum distance between Vin and Cin, approximately? Why the input capacitor should be closed to the Vin pin?

Also, I know that output capacitor should be placed to the inductor closely. How long is the best and maximum length between Inductor and output capacitor?

Thank you!

  • Hello Garam,

    Which buck converter are you using in your design?

    Regards,

    ~Leonard  

     

  • Hi Garam,

    As Leonard implied with his question, these distances are highly depend on current levels, switching speed, and frequency - however, it is unlikely anyone can give an exact distance with which the circuit will/will not work.

    When laying parts out on a PCB, it is best to think about all the various current loops and waveshapes (slew rate or dI/dt transitions).

    Although we can't specify exactly what distance will/won't work, I can say this: It is VERY important that the input capacitor be placed as close as possible to the buck switching MOSFET (it sounds like you're working with an IC that has the MOSFET internal and connected to the Vin pin).  The reason this is critical is because the current waveform for this input capacitor is similar to a pulse train.  During the transitions of this pulse train, the current has a very high slew rate (dI/dt).  Any stray inductance between the input capacitor and the MOSFET will cause the voltage to ring excessively.  Remember the old equation for the voltage across an inductor: V = L (dI/dt).

    As you mentioned, the placement of the output inductor and output capacitor is also critical, but a little less critical than the input capacitor described above.  Assuming continuous operation (i.e., the current never goes to zero), the current waveform for the inductor and the output capacitor is a continual ramp (up & down) waveshape.  The slew rate of a ramp (dI/dt) is not nearly as high as the slew rate during transitions of a pulse train - this is why it is slightly less critical.

    Let us know if this helps,

    Jim

  • Thank you Jim and Leonard,

    Your explain helps me a lot, Jim.

    It sounds like input cap should be closed to the MOSFET, not a Vin, to make a short length trace between MOSFET and Input cap because of voltage ringing.

    Is this correct?

    "The slew rate of a ramp (dI/dt) is not nearly as high as the slew rate during transitions of a pulse train" This part is a little bit hard to understand, could you please explain more detaily?

    Thank you

  • Garman,

    In general, yes, you are correct, but I'd be curious where you may see an app note indicating otherwise.

    Please check out page 5 of this app note: http://www.ti.com/lit/an/slva057/slva057.pdf

    If you take the derivative of the MOSFET current with respect to time (dI/dt), you will see huge spikes during the transitions.

    However, if you take the derivative of the Inductor current with respect to time (dI/dt), it will be a much lower value.

    -Jim