• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 445 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About Buck Layout Review

Gary An
Intellectual 440 points
Other Parts Discussed in Thread: LMR23630, LMR33630

Hello all,

I read all the documents about layout and I tried to make schematic and layout with LMR23630 on the EasyEDA.

My desire conditions are, Vin=12, Vout=3.3v, Iout=3A.

The efficiency is 85% at that condition, so I could get Iin is around 0.7A.

I tried to divide PGND and GND, is this correct? (PGND is for the input capacitor ground, GND is ground except input capacitor)

I could see that 3A(output current) should be 0.9mm(35.5mil) conductor width and 0.7A(input current) should be 0.15mm(5.9mil) conductor width at temp set 20 degree on the below graph.

I set the 35.5mil conductor width for the 3A traces, and 5.9mil conductor width for the 0.7A traces, is this correct?

How much value should I set the vias diameter?

Could you please advise me how it can be improved my layout?

I need your help earnestly.

I attached the layout files(EasyEDA, Altium).

8816.Layout.zip

  • 0
    TI__Guru 65035 points

    In general I would follow the layout in the data sheet.

    Here are some comments:

    1. Do not separate AGND and PGN; tie together and merge with DAP as in data sheet layout.

    2. Do not use thermal reliefs.

    3. It is good to have a complete ground plane on top and bottom connected with vias to get the heat out

    4. I would not go any less than 10mils on any trace

    5. Move CBOOT closer to device and increase width of trace to pin.

    6. Move CVCC closer to device and increase width of trace to pin.

    7. Ground CVCC direct to top/bottom ground plane; with ground vias

    8. Use wide plane/trace for VIN, similar to your Vout connection.

    9. Swap RF1 and RF2 so RF2 is closer to device and closer to AGND point.

    10. Concern is not so much with current or resistance capability of traces but providing low inductance and resistance for power connections.

    11. Your inductor looks a little small ?  Be sure it can handle the current limit of the device and has low resistance for good efficiency.

  • 0 in reply to Frank De Stasi
    Intellectual 440 points

    Thank you so much Frank,

    I have few questions about your comments.

    1. I learned that PGND and AGND should be separated, because large current goes to the PGND. If PGND and AGND are not separated and large current goes to PGND, then ground voltage level of PGND and AGND are different, it might cause of ringing and other noise. Is this not correct? Can you please explain why the PGND and AGND should not be separated? 

    2. I just put copper and the thermal reliefs came out, I do not know why the thermal reliefs came out. Can you tell me how I can remove the thermal relief? Should I remove the copper around the thermal relief?

     

    And I put the ground via inside of the Buck IC for the thermal. Is this correct?

    5, 6. The reason I have to increase width of trace of Cboot and Cvcc is the current through the Cboot and Cvcc is high?

    I thought that the current of Cboot and Cvcc traces are not high(under 1A), so I thought 10 mil is enough. Should I increase the width more?

    8. Wide plane for Vin means "increase the surface of PGND"? and I calculated that the input current is 0.7A, so I thought that 10mil of Vin trace is fine. Should I increase the width more? Could you please explain the reason, if yes?

    Thank you so much!

  • 0 in reply to Gary An
    TI__Guru 65035 points

    The power and agnd are separated inside the IC, so they need to be connected outside.  So, preventing

    the noise pertains to inside of the device.  

    There should be a setting on your CAD tool that allows you to use direct connection rather than reliefs.

    It is good to have the thermal vias under the device.

    There are moderate current pulses in the boot and vcc cap, and you need low inductance on this trace.  10mil or 20mil is OK width for these.

    You need wide traces for the input, to reduce inductance and resistance.  Not so much for current density.

    You can also look at LMR33630 data sheet for another example of PCB layout.

  • 0 in reply to Frank De Stasi
    TI__Guru 65035 points

    Hello

    I am closing this post.

    Thanks