• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 518 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65094: TPS650942 RSMRSTB output glitch

Edward Lee
Intellectual 1655 points
Part Number: TPS65094

Hi Sir,

      My customer recently encountered a problem with the RSMRSTB output.

      During startup, there will be a glitch at the RSMRSTB output of TPS650942.

     

  They found that it is related to the delay between the supply volage (VSYS) and the enable (PMICEN).

  If the PMICEN is asserted high right after the rising of VSYS, the glitch occurs.

  If adding a delay after the rising of VSYS, the glitch disappears.

  Are there specific timeing requirements beween the supply voltage and the PMICEN?

 

Thanks

Sincerely,

Edward

  • 0
    TI__Mastermind 30310 points

    Edward,

    When is power applied to V5ANA? There is strict timing requirement between V5ANA and VSYS, but I cannot see in your scope shots when any of the input signals are applied.

    Please share scope shot using all 4 channels:

    1. RSMRSTB
    2. VSYS
    3. PMICEN 
    4. V5ANA

    And then I can provide feedback on what might be causing your issue.