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BQ25505: Ultra-low power operation

Part Number: BQ25505

We designed an energy harvesting device that will generate 0.6V at 100nA (similar to another question on the forum). We could stack several devices to get >2V but are not sure if we can support the BQ25505's total power input requirements. Have several questions about the quiescent current, Vin and Pin.

  1. Quiescent current: Average is 325-400nA when Vin is 0V, and Vstor is 2.1V. 

  1. Over what time period is the 325nA average taken? 

  2. Is this current approximately continuous or is there a duty cycle? If duty cycle, is it fixed or programmable?

  3. Does the BQ circuitry draw that current from any source tied to Vstor (such as a supercap on VBAT_SEC meant to service the load)?

  4. If VSTOR < VSTOR_CHGEN, and Vin is 0 or <100mV, how does this affect quiescent current? Is the circuitry effectively ‘off’ at this point until Vin>Vin(CS)?

  5. If the circuitry draws current from VSTOR, and the circuit is effectively off when VSTOR<VSTOR_CHGEN (questions 1c and 1d), can we prevent the circuitry from being powered by VBAT_SEC when VSTOR>VSTOR_CHGEN and Vin=0?

  • Quiescent Current Range: 

    1. With the duty cycle time in ms, my assumption is that the quiescent current draw is effectively 325nA, but what is the actual range of the quiescent current (0-1uA for example)? We could handle 1uA, for example, with a very low duty cycle (e.g., 1% or less).

    2. What is the duration of the current draw at the high end of that range (for example, 0.2ms at 1uA)?

  • Datasheet changes

    1. The datasheet for the BQ25505 for the evaluation board we bought has been revised since then (version dated September 2013).  The most recent revision (Rev F dated March 2019) has some important differences.
    2. Vin for cold start changed from 330mV(MIN) to 600mV(TYP)/700mV(MAX). Does this reflect a correction to the specifications or is it a design change? If we order more chips, will they have a 700mV worse case for cold start/normal charging?
    3. Same question for minimum power input for cold start and normal charging. Old Pin was 5uW, but the most recent version says it’s 15uW.
  • Voltage and Power Requirements: To make sure I fully understand the Vin and Pin requirements - 

    1. The Rev F datasheet states Vin of 600mV (TYP). However, my BQ25505 evaluation board successfully enters the cold start and booster charging state with just 340mV. So, again, does the datasheet change reflect a correction to the cold start Vin voltage spec or is this a chip design change (i.e., higher cold start V) that must be considered if we use current production BQ25505 chips?
    2. Is the Pin minimum of 15uW (per new DS) a hard number? For example, 15uW would require Iin of 45uA @ 330mV.
      1. If we managed to design with an input of >0.6V but with current less than 300nA, could we still meet the Pin requirements using the formula in the datasheet?
      2. If 15uW is a hard minimum for Pin, then that is effectively an Iin minimum of 8uA (or 25uA new) @ 0.6V.

Thanks for your help in understanding how the BQ chip works and if we can utilize it in our design. 

 

  • Hi Larry,

    Regarding 1, average time for the Iq measurement is about 2-3 seconds.  All measurements are for the boost converter not switching.

    Regarding 2, measured Iq includes the VRDIV sampling for 4ms every 64ms, during which time the Iq is slightly higher.  Otherwise, Iq is constant.

    Regarding 3, yes, VSTOR powers the chip from whatever source is at VSTOR = VBAT if the internal PFET is closed.

    Regarding 4, when VSTOR < VSTOR_CHGEN, the main boost circuitry is off so VSTOR doesn't pull Iq.  The charger tries to raise VSTOR and VBAT through the internal PFET body diode to VSTOR_CHGEN using the cold start circuit, which is a very low efficiency boost converter.  We did not characterize its Iq.

    Regarding 5, when VSTOR>VSTOR_CHGEN>VBAT_UV, the PFET between VSTOR and VBAT automatically turns on and allows the storage element at VBAT_SEC to power whatever load is at VSTOR, including the IC itself.

    Regarding Iq range, see  d/s figures 8 and 9 for average Iq range.  Keep in mind these are for the boost converter not operating (i.e. no input power source).  When switching due to input power source, the Iq is higher in order to drive the boost converter FETs.

    Regarding datasheet change and VIN, PIN requirements, there was no spec change.  We found an error in our production testing and discovered we can not consistently produce devices that startup with cold start down to 330mV and with such low PIN.  Some devices operate down to 600mV in cold start, especially after sitting for long periods without power, but we cannot warranty that all devices will.  The PIN_CS number is typical value and is not tested in production.  I have seen the device operate in cold start with much less than 15uW.  The value is more of practical number in order for cold start to raise VSTOR =VBAT_SEC to VSTOR_CHGEN in a reasonable time frame. 

    In order to exit cold start (i.e. charge VSTOR up to VSTOR_CHGEN) I always recommend to isolate any resistive loads connected at VSTOR using an external PFET with gate drive by /VB_SEC_ON.  Also, you have to consider the leakage current of your storage element, especially if it is a super cap.  

    Regards,

    Jeff