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TPS7A47: adjustable Vout=Vin-0.3V LDO power design with TPS7A4701

Part Number: TPS7A47

Hi there,

We met some trouble when design a special LDO power as follow.

This specific LDO circuit is placed right after power-in port (battery or adaptor) and  is aimed to suppress 800KHZ switching noise generated from other DC/DC modules in system.

(1)Vin = 14.4V(battery) or 19V(adaptor),

(2)Vout is required to approximately follow Vin:  Vout = Vin - V_drop,   V_drop should be small to reduce power loss, and is expected to limite within (0.2~0.4V), the exact number is not important, but we sat its typical. = 0.3V.

(3)I_load max = 1A or so.

(4) PSRR > 40dB at 800KHZ

We built an LDO prototype with discrete components (mosfet and amplifier) , but the PSRR is not as good as expected. And we think better to use off-the-shell LDO IC to do this. Hope TI experts could help on this. Thanks very much!

  • Hi Yi,

    The TPS7A47 has really good PSRR across a wide bandwidth, However, for minimizing V_drop, any LDO's PSRR performance degrades. See the below plot from the TPS7A47:

    When an LDO gets into dropout, it is working like a load switch. In this mode of operation, the only filtering it can provide is a function of the effective resistance of the LDO and COUT

    So maintaining a V_drop of ~800mV would help to get the filtering you are looking for.

    Note: Thermally at 1A with a 500mV drop, there is 500mW of power dissipation. The thermal performance of the TPS7A47 is quite good so with a TJA of 32.5C/W. The temp rise of the die would only be 0.5*32.5 or ~16.3C rise above the PCB ambient.

    I hope this answers your question.

  • Thanks, John, you infomation on PSRR vs V_drop is helpful. 

    Do you have any suggestion on how to implement setting Vout = Vin - 0.5V (or 0.8V) ?  Becasue Vin can battery=14.4V or adaptor=19V, connecting the FB pin seems a little tricky. Thanks.

  • Hi Yi,

    Something like a tracking LDO seems like what you are looking for. The TPS7B4254 regulates to the applied reference. Here is a quick schematic and simulation:

    I will have to check with design to see if the NR pin of the TPS7A47 can be over-ridden to turn it into a tracking LDO. 

  • Hi John , thanks for introducing trakcing LDO. I will wait for you info about whether NR pin of the TPS7A47 can be over-ridden to turn it into a tracking LDO.

  • Hi Yi,

    I confirmed with our design team that the device will operate if you drive the reference externally as described above. We have not tested this configuration so not sure at all as to how well it will perform. 

    Do you have an EVM that you can try?


  • Hi John, thanks for confirm NR pin. 

    But we do not have the tps7a4701 EVM to try this configuration, whose PSRR performance is unkonwn as you mentioned.May be we should borrow an EVM to do some bench test.

    Another concern is, the real load current was measured recently as below picture, the average current is less than 1A (total power consumption < 19W) , but the peak transient current could be as high as 4.5~5A in an aprrox. repetitive periode of about 12us.  Can TPS7A4701 handle this kind of load condition ? Thanks again.

    1. Current waveform Channel4 

    2. zoomed in waveform (more details)

  • Hi Yi,

    THe TPS7A47 has a current limit and thermal shutdown. If the load current exceeds the current limit, that would first engage followed by a thermal shutdown to protect itself.

    You should be able to order and EVM. If you can't, I can try to get you one.


  • Thanks for helping, John. I will try to get one EVM from local agency company. some more questions to consult.

    1. As you see the waveform (Channel 4) above, 2. the load current is not constant vaule but intermittent. from first pic, you can see in 150ms peorid there is 125ms I_load = 0 and 25 ms I_load is rippling as pic 2 shows, the ripple cycle in every 25ms is about 12us and nearly 5A. 

    It is a kind of fast transient current spike, and I am not sure 4701 would be able to respond in time? or how fast (how short the current spike lasts) could 4901 response?  we will have to  test on board, but it would be better if TI has relevant data or info to reference. 

    2. For its current limit behavior : IF during test we intentionally set a large CONSTANT I_load of 5A, we would see the I_out be limited to 1.26A(typical) according to section 7.3.1 in datasheet, and I assume the Vout will drop drastically. As time pass,  4701 will became hotter and finnally trigger its thermal shutdown. After shutdown it will become cooler, and when temp cools to below 150°C, it will work again but still in overload situation if 5A load is still ON. As this cycle goes on, the device will eventually damaged because of overheat. Is this perception correct ? 

    Thanks again.