TPS55165-Q1: Layout Considerations

Tom Lightning

Part Number: TPS55165-Q1

Hi,

since my last layout for the TPS55165-Q1 didn't work well, i'm trying to develop a new layout. Regarding the layout of the TPS55165Q1 in almost all threads are mentioned the pcb layout of the evaluation board and the application note SLVAEJ2. Due to the difference between the layouts of the evaluation board and the layout of fig. 4 and 6 from the application note, I do not know which layout i should consider for my own layout. So should i rather use the layout of the evaluation board or the other one? In my opinion the design mentioned in the application note manages the PGND and GND connection better than the evaluation board, because the analog ground is exclusively connected to the power ground by the power pad.

In order to achieve a good performance I should consider at least two solid GND copper planes in addition to the quite solid gnd area on the side on which the TPS55165Q1 is placed, am I getting this right?

Best regards,

Tom

over 5 years ago

0 Helen chen over 5 years ago

TI__Mastermind 40080 points

Dear Sir,

EVM and the app note from different author.

For the AGND/PGND, Vreg/Vreg-q connection, you can refer to the app note.

0 Tom Lightning over 5 years ago in reply to Helen chen

Intellectual 305 points

Okay. I have done a new layout, which can be seen in the following figures. The green and brown copper planes are on GND potential. Is it permitted to route the VINL and IGN signal like this? Or should the VINL be routed separatley? Do you have any further advise regarding to the layout?

Thanks!

0 Helen chen over 5 years ago in reply to Tom Lightning

TI__Mastermind 40080 points

Dear Sir,

Your VINL VINP connection looks strange You can refer to the App note figure3. VINP is power pin, you pour it with power while VINL need to be carefully single point connected.

TPS55165 is very sensitive. especially when it works in the boost mode. currently output cap connection is a little bit strange. I posted the EVM sch and pcb. Please strictly lay the pcb according to it if you put the inductor and boot strap cap on the top layer.1541.HVL143B_Main.SchDoc 8168.HVL143B_PCB.PcbDoc

0 Tom Lightning over 5 years ago in reply to Helen chen

Intellectual 305 points

Hello,

what looks strange about the VINL connection? To me it is connected to the VINP potential in one single point. Or should I route the IGN signal separately from the VINL signal? I can't redesign the layout of the evaluation board, because the trace to the VINL signal would violate rules regarding to clearence. Furthermore I am not allowed to use caps larger than 0805, because the risk of cracks in the ceramic is increased. Therefore I can't design the output capacitors one to one to the evaluation board.

Best regards,
Tom

0 Helen chen over 5 years ago in reply to Tom Lightning

TI__Mastermind 40080 points

Hi Tom,

Sorry, I made a mistake just now. The VINL and IGN connection is OK.

If you layout it in Altium designer, could you please share the pcb layout with us for a review? We can discuss by email.

0 Tom Lightning over 5 years ago in reply to Helen chen

Intellectual 305 points

Hi Helen,

I'm using Target as CAD program. I dont know wether Altium can handle the format .T3001. Would you say that this layout is worth testing?

Best regards,

Tom

0 Helen chen over 5 years ago in reply to Tom Lightning

TI__Mastermind 40080 points

Hi Tom,

I can open it with T3001 viewer, I want to have a look since this part is quite sensitive.

0 Tom Lightning over 5 years ago in reply to Helen chen

Intellectual 305 points

Hi Helen,

please give me an e-mail address so that I can send you the target project.

Tom

0 Helen chen over 5 years ago in reply to Tom Lightning

TI__Mastermind 40080 points

Hi Tom,

Please accept my friendship request, I'll send the email to you.

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TPS55165-Q1: Layout Considerations