• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 278 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM25122-Q1: LM25122-Q1 PCB layout

David Trotter
Intellectual 730 points
Part Number: LM25122-Q1

I have a question about PCB layout for the LM25122-Q1. 

On the reference designs

http://www.ti.com/lit/df/tidrvn6/tidrvn6.pdf

A copper area under and around the LO switching MOSFETS Q3 Q4 Q7 and Q8 is present through all the layers including the ground plane and stitched together with VIAs. 

Is this recommended? Surely a complete ground plane layer is beneficial for reducing EM emissions. What is the reason for this large copper area on all layers? 

Thanks

David

  • 0
    TI__Guru* 78270 points

    Hi David,

    Thank you for consider the LM25122 solutions.  These are for head dissipation through the PCB.  Without them, you may have to add heatsink to the FETs. You are right that the FET drain pad is the switch node and it can affect EMI, and it can be mitigated by applying additional shielding.  Anyway, for you final product, you need to trade off between EMI and thermal management. 

    Thanks,

    Youhao Xi, Applications Engineering