• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 454 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ25898D: About HiZ state

user777540
Expert 1020 points
Part Number: BQ25898D
Other Parts Discussed in Thread: BQ25890

Hello,

I have 4 questions about HiZ state.


1. It is said in Section 9.2.3.1 that VBUS is less than IVBUS_HIZ during the HiZ state.
Please tell me the current value of IVBUS_HIZ.


2. If you set EN_HIZ of REG00 to 1-Enable, will it be in HiZ state?


3. If set to Enable, will it stay in HiZ state until it is set to Disable?


4. Is it possible to detect Input removed (VBUS_GD) in the HiZ state?

Can I access the register via I2C?
Is it possible to output an interrupt?

best regards

  • 0
    TI__Guru**** 166176 points

    Hi,

    Regarding 1, the IVBUS(HIZ) spec is the second item in the electrical specs table on d/s page 8.  It is 15 uA typical and 35 uA max with VBUS=5V.

    Regarding 2, if you set EN_HIZ=1 and disable the watchdog timer, the IC remains in HiZ state until it is set back to 0 through I2C or VBUS is removed and replaced.

    Regarding 3, see 2 above.

    Regarding 4, yes.  The VBUS_STAT and PG_STAT  bits are still functional in HIZ and accessible via I2C.  INT for VBUS removal is also functional.

    Regards,

    Jeff

  • 0 in reply to Jeff F
    Expert 1020 points

    Hello,

    Regarding 2), if the VBUS is removed and then reattached, will the EN_HIZ register value automatically switch to 0?

    The following are additional questions.

    Is DSEL low when EN_HIZ register is set to enable after DCP detection by DPDM detection?

    best regards

  • 0 in reply to user777540
    TI__Guru**** 166176 points

    Hi,

    Yes, VBUS reattach returns EN_HIZ to default 0.

    Regarding DSEL, from pin description on page 6:

    During input source type detection, the pin drives high to indicate the bq25890 D+/D- detection is in progress and needs to take control of D+, D- signals.

    When detection is completed, the pin keeps high when DCP, MaxCharge or HVDCP is detected. The pin returns to low when other input source type is detected

    Regards,

    Jeff