This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UC3854A: INPUT CURRENT IS DISTORTED AND HAS LARGE SPIKE AT ZERO CROSSING

Part Number: UC3854A
Other Parts Discussed in Thread: UC3854

Hello, I started to use UC3854ADW from 2000 in many of our products for Power Factor Correction. The power range is from 500W to 5KW in a single phase power system. In the past 18 years, the input current waveform was nearly perfect, it is almost the same shape of input voltage, and the quality is very stable.  However, recently, the input current waveform was distorted when we compare with the controller UC3854A  made before 2018. The Power Factor is dropped sharply after 2018. We see spikes when the current happened at zero crossing(Figure 1). The harmonic current is over the limit of 1000-3-2 class A. We confirmed if UC3854ADW made before about 2018(do not know the exact date), the input current was  perfect(Figure2). I would like to know if TI changed the design/process recently. And if other customers have the same complain.

Figure 1: Channel 3 purple current has large spike at zero current crossing. The PFC controller at this figure was made in 2019. 

             Ref:   Channel 1 is AC Input voltage at 220V.  Channel 3 is AC input current. 

         

Figure 2: Channel 3 purple waveform is the input current has no spike at zero current crossing. The only difference is the chip UC3854A was replaced from the newer date code to the old date code one(2014). All of the rest components are the same.

  • Hello Hong,

    Its hard to say what is happening without being able to review the schematic.

    At the zero crossings the controller has difficulty matching the current amplifier output with the multiplier output.
    This is because the voltage across the inductor is very low and so the converter is unable to deliver the required current demanded by the multiplier.
    This results in the current amp saturating.
    Once the input voltage rises high enough the current overshoots because the amplifier is saturated.
    This may be causing the spike around the zero crossings.
    The current recovers when the amplifier comes out of saturation.

    So thats what I think may be happening. If you post the schematic with the component values I may be able to offer some more help.

    Please post as a pdf attachment since it is impossible to read an embedded image.

    Regards

    John

  • hi John,

    For the PFC sectoin, the peak power is 3kW. I use 1301079 and 1301094  as attachments. 1301079 is the PFC control module and 1301094 is the mother board.  It is a little bit hard to read pin to pin. Please let me know if you have any questions about the schematic. 

    4118.1301079.pdf

    6153.1301094.pdf

    Regards, 

    Hong

  • Hi Hong,

    It looks like this issue is being answered through email . I will need to close this post in order that the issue is handled in the most efficient manner.

    Regards

    John

  • Hi John,

    Do you have a chance to review the schematics I posted ? My PFC operating frequency is 42kHz. The PFC choke inductance is 600uH. All values in the schematic are exactly follow up your design instruction sheet. 

    As you mentioned above, the zero crossing distortion occurs just after the AC line input has crossed zero volts. At this point the amount of current which is required by the programming signal exceeds the available current slew rate. When the input voltage is near zero there is very little voltage across the inductor when the switch is closed so the current cannot ramp up very quickly so the available slew rate is too low and the input current will lag behind the desired value for a short period of time. Once the input current matches the programmed value the control loop is back in operation and the input current will follow the programming signal. During this transition, the current amp may saturating then caused a spike. 

    My questions are :

    1. How can I prevent the current AMP to get into saturation? Which pins should I adjust to ?

    2. I found if I reduce the value of R15 and R25 from 10k to 7k. I can reduce the spike a little bit. But is not still enough. 

    2. Does pin 6 Iac affect this cusp distortion? Should I add some bias to this pin to avoid the situation?

    3. This weekend, I ordered some old date code chips, from 2012, 2016 and 2017. All have good input current waveforms without seeing this Cusp distortion spike.  Why do I not see this spike where I just switch the PFC controller from the new date code chip to  the old date code chip? 

    4. Can I have your email address so that we can discuss more? 

    I am looking forward to your reply.

    Hong

  • Hi Hong,

    Sorry about taking so long to reply. I was out of the office for a while.

    Anyway I reviewed your schematic and I think the circuit was designed for the UC3854 part.

    The UC3854A does not require a DC offset on the ISENSE pin.

    In your schematic you have 30mV on this pin. This will cause the current amplifier to saturate low around the zero crossings.
    When the CA comes out of saturation it overshoots and I think this is causing the spikes in your waveform.

    Please remove R38 from your pcb assembly and retest.

    Let me know how you get on.

    Regards

    John

  • Hi John,

     

    The suggestion for removing R38 does not work. I removed R38,  the zero cross spike  is still there.

     

    However, I am making progress by double the Iac current which seems help.

    I think at the data sheet of UC3854A page 8, the recommended Rac value1.53M is not optimized.  I found Rac is very important for  this spike. Our current design is based on Rac=1.53M ohm which limits the Iac < 250uA at high line. According to TI application note Slua263 page 2, it says sometimes, the Iac is desirable to increase the current as high as 500 uA. To do so, the Rac should be around 750k ohm. With this change, I can get very good input current waveform without this spike. Can you please double check which recommendation I should follow up? If 500 uA is needed in order to get a better signal to noise ratio, I suggest TI to update the official data sheet.

     

    Regards,

     

    Hong

     

  • Hi Hong,

    One other comment I have is that your design has a 20M Ohm connection from VBRIDGE+ to the timing capacitor CT.

    What is the purpose of this and have you tried disconnecting this connection ?

    Regards

    John

  • hi John,

    The PFC main switch frequency is around 40kHz. This 20M ohm resistor from Vbirdge is for adding around +/-2kHz range at main switch for Frequency Jittering  to reduces EMI noise. It has been confirmed with/without this 20Mohm resistor, the input current waveform is not affected.

    Hong

  • Hi Hong,

    I understand. But this,together with the DC bias on the current amp input , is another example of the UC3854A being operated in an characterised environment.
    Without a proper signal on ISENSE+ and ISENSE- it will be very difficult to generate the correct pwm pattern
    There seems to be a lot of filtering on the current sense input and it may be that this signal is getting corrupted before it gets to the controller

    There are also zener diodes on CAOUT and PKLMT.
    These parts were used with the UC3854 but are not used on the UC3854A.

    Regards

    John

  • Hi John,

    I removed all additional components around ISENSE+ and ISENSE and those Zener diodes. All do not affect the spike of  AC input current. Again, reducing Rac value to increase the Iac current,  and adjust Rmo value accordingly  can improve the input current a lots.  Did you have a chance to read  TI application note Slua263 page 2?

    Regards,

    Hong

  • Hi Hong,

    I read the app note and I cant  comment on it since there is no data available to verify the single claim.
    I am very wary of operating an ic outside of its data sheet parameters .
    In your case you have a certain failure rate and if you operate the device above the ic test parameter characterisation range then I think 
    you may well generate a higher failure rate .
    My opinion is that there is a noise pickup issue on the input to the current amplifier since this has input signals in the millivolt range and the pfc is switching hundreds of volts over hundreds of nano seconds.
    IAC is low frequency a current signal input and is much less prone to noise pickup.

    Regards

    JOhn

  • Hi John,

    The app note is also officially published by TI. It suggests designers to double the input current from 250mA to 500mA. And also, please check all your typical application circuits, all are using 500-600mA range. Can you please tell me why?

    By the way, although the Iac current is a 100-120Hz low frequency signal, when I double the Iac current, I need to reduce Rmo value half accordingly. Since Rmo is calculated from Iac.

    This reduced Rmo value can affect the current amplifier immediately at PFC frequency level. This is the reason that I can see the cross spike can be reduced.

    I would like to repeat my problem. If the chip made before 2017, I do not see the problem. However, after made from 2018, I see all have the same issue. It is not higher or lower failure rate. It depends the chip batch. I doubt if TI changed the manufacture process or used wrong profile. For example, used UC3854 profile to make UC3854A.  I have sent two problematic ship(date code 2018) to TI for asking failure analysis at April. Until today, I still can not get any report. It takes too long,

    Hong

  • Hi Hong,

    Since no other customer has reported this issue and you are convinced that operating the part outside of its characterised parametric data
    then there is very little I can offer in the way of suggestions.

    Regards

    John

  • Hi John,

    I understand. Thanks for your help anyway.

    Regards,

    Hong