LM4050QML-SP: LM4050QML-SP and ADS1278-SP

Hey Dinakar,

I am the engineer that specializes with the LM4050QML-SP

We have a resistor calculator you can use here:

https://www.ti.com/tool/SHUNT_VOLTAGE_REFERENCE_RESISTOR_CALCULATOR

The data sheet provides suggestions to the amount of current needed to regulate the LM4050QML-SP:

One thing I will add is that the radiation data was taken with 60 uF of capacitance and 100 uA of IQ. This makes the suggested IQ 100 uA and CL 60 uF.

I have no graphs to provide load response for CL = 60 uF thus I do not have information to share on the step response, but unless the response is large the response should be minimal.

As far as if you can achieve 16-bit resolution, I cannot comment, but can attempt to get a response from someone who specializes in ADCs.

Thanks,

Daniel

Hi Daniel,

Thanks for the information.

Average reference current drawn by the ADC is 73 uA (ADC reference input impedance with 128 kHz sampling rate is 34.3 kohm and its reference voltage is +2.5 V). Input voltage to the regulator is +5 V regulated supply. The calculated external series resistance for 5 mA regulator current is 500 ohm (since the ADC current is negligible compared to the regulator current). But, how stable is the regulator output voltage for the ADC switching currents? If it varies and not meeting my bit resolution, can you suggest any space qualified +2.5 V series regulator?

Thanks

Dinakar

Hey Dinakar,

Our datasheet shows a typical plot of the output impedance of the LM4050QML-SP with a 1 uF capacitor.

What this means for having a 1 uF capacitor is that with 10-30 ohms of output impedance at peak I can multiply that by the current transient to see what would happen to a current transient that hit at exactly the 10 kHz frequency.

30 Ohms*73 uA ~= 2.2 mV.

With 60 uF of capacitance its likely this is lower, but it should give you an estimate to the maximum transient you should see.

Our other popular reference is the TL1431-SP if you would like to check it out.

Thanks,

Daniel

Hi Dinakar,

I ran a simulation with the LM4050, taking into account the output impedance (combination of LM4050 and output capacitor) and the switched input load that the ADS1278 presents.  Using 10uF of REF capacitance or less, the resulting settling time will limit your resolution to less than 15b.  Using at least 47uF, the simulation suggests that you can achieve 16b settling on the reference input.

Since the output capacitance and ESR of your reference cap will change the overall response, your results may vary, but the simulation indicates that this combination will work.  If you increase the modulator rate by a factor of 2 or more, you will not likely be able to settle with any combination of output capacitance.  

Another option would be to use a reference buffer, which will provide some additional margin on settling time, and will allow you to sample at a higher rate if later needed in your system.

Regards,
Keith Nicholas
Precision ADC Applications

Hi Daniel,

Thanks for the information. I will check it.

Dinakar

Hi Keith,

Your simulation is very useful for me. What is the impedance value (regulator and ESR of the capacitor) you have used in the simulation?

Also can I use LMP2012 as a refrence buffer for 256 kHz sampling rate and 16-bit resolution?

Thanks,

Dinakar

Hello Dinakar,

I modeled an MLCC ceramic capacitor; 47uF with a typical ESR of 50milliOhm.

I also took a look at using an LMP2012 as a reference buffer.  For 256kHz, I think you can easily get to 16b resolution, based on simulation results.  The simulation results also predict that you can get full specified performance when operating at 256kHz or lower modulator sampling rate, but testing in the lab would be needed to confirm this.

Below is the circuit that I used; it uses a 10uF output capacitor and a dual feedback topology for stability.

Regards,
Keith

Hi Keith,

Thank you very much.

What external series resistance value has to used between supply voltage (+5V regulated) and the LM4050 if the op amp is not used for driving ADC ADS1278? The ADC is configured for reference input impedance of 32.2 kohm (128 kHz sampling rate, 8 active channels).

Thanks

Dinakar

Hello Dinakar,

I used a 500ohm resistor, which results in 5mA of bias current in the LM4050-2.5 operating from a 5V supply.

Attached is the TINA-TI simulation file if you would like to look at it in more detail.

Regards,
Keith

/cfs-file/__key/communityserver-discussions-components-files/196/LM4050_5F00_ADS1278_2D00_SP_5F00_47uF-TINA_2D00_TI.TSC

Hi Keith,

Thank you very much for the file. This is what I need. Now I can do my own simulations with different configurations.

Also please tell me that how did you choose 228pf in your simulations as the adc refrence sampling capacitor?

Thanks

Dinakar

Hello Dinakar,

You can estimate the equivalent input resistance as Req=1/(Cin*Fm).

Cin=input capacitance

Fm=modulator frequency

Rearranging the above equation, Cin=1/(Req*Fm) = 1/(34300*128000)=228pF

This number assumes all 8 data converters are active.  For N converters, the approximate input capacitance will be Cin=228pF*(N/8)

Regards,

Keith

Hi Keith,

Thank you. I was using Req=1/(2*pi*Cin*Fm) for estimating Cin. Now it is clear for me.

I have a couple questions.

1) I do not have MLCC type capacitor. I have Tantalum type capacitor with 1 ohm ESR. I have simulated with it. It has 11mV peaks and settled to 65uV.  What is my settling error in this case? Since it settled to 65uV with in the acquisition period, can I use reference voltage as 2.5V+65uV for my calculations? Please clarify.

2) I calculated clock jitter requirement for the adc using the below formula.

SNR = -20log(2*Pi*Fclk*Tj)+10log(OSR)

Here, SNR = 96 dB (for 16-bit resolution)

Fclk = ADC clock input = 512 KHz (Fm*4)

OSR = Over sampling ratio = 128

Tj = Clock jitter

The maximum clock jitter shoul be 55 ps.

Also, my clock source is 1 meter away from the ADC. So I want to use a differential clock driver for the ADC. Can I use LVDS transceiver DS90C031/32  combination for this application? Please suggest.

Thanks

Dinakar

Hello Dinakar,

In order to achieve performance to a specified number of bits, we have found that the input signal error at the end of the acquisition period be less than 1/2LSB.  In the case of ADS1278 using a 2.5V reference, 1LSB=2*2.5/2^16=76.3uV.  1/2LSB is then 38.15uV.  65uV of settling will result in ADC performance closer to a good 15b ADC, not 16b.

You can experiment with different capacitor combinations to lower the overall impedance.  For the bulk capacitor, you stated the use of a Tantalum, which is fine.  Add an additional low ESR ceramic capacitor of at least 0.1uF which should help with overall settling.

For clock jitter, which digital filter option are you using?  The OSR is the ratio of the input sampling rate (modulator rate Fmod) to the output data rate (ODR).

OSR = Fmod/Fodr

This value is determined by the digital filter setting on the ADS1278, and can be either 64 or 128.

The input frequency for the SNR equation due to jitter is the actual input frequency of the signal you are trying to measure, not the input clock frequency.

In your case, your input clock is 512kHz, and assuming you are using the high resolution filter option (OSR=128), the output data rate will be 1ksps, which limits the maximum input signal frequency to 500Hz.

The resulting maximum jitter requirement will then be much higher, in this case, 44.9nS.  Just about any decent clock source can easily meet this requirement.

DS90C031/32 will not work directly with ADS1278.  The DS90C031/32 are 5V logic levels; ADS1278 supports a maximum logic voltage of 3.6V.

Regards,
Keith

Hi Keith,

I have simulated with 47 uF and 0.1 uF combination as you suggested. Now, peak value of the signal reduced to 73 uV from 11 mV. The signal value at the end of acquisition period is 63 uV. Please see the attachment. It is almost same as in the previous case without 0.1 uF capacitor. Is there any benefit in using the additional capacitor 0.1 uF? Also, can I get 16-bit resolution if I use the reference voltage as 2.5 V + 63 uV instead of 2.5 V while converting the digitized data to analog signal?

It is very clear for me now regarding clock jitter calculation. I misunderstood the equation.

You are right. DS90C031/32 combination will not work with ADS1278. Can I use SN55LVDS31/33 combination?

Thanks,

Dinakar

LM4050_ADS1278-SP_47uF TINA-TI - For clarification.TSC