TPS543B20: schematic check

Hi Zoe,

I have several comments on the schematic:

1. If this is for a prototype board, I recommend adding a 2.2nF-10nF 0402 input capacitor from PVIN to PGND and placeholders for a switch node snubber 1nF + 1ohm resistor which help reduce switch node ringing. You can omit them in the final design if testing shows they are not needed to meet switch node ringing targets and of course to stay below abs max ratings. At 9Vin, it is unlikely any ringing would be close to datasheet limits, but it is good to have placeholders for testing purposes. They could also use the same board to evaluate other conditions with more flexibility this way.
2. R2 should be closer to 48kohm for OCP = 24A
3. 1uH gives about 1A Ipp ripple at 1MHz.. This is pretty low ripple for a 15.5A design. They could consider using half the inductance to lower DCR and increase full load efficiency, and even reduce solution size with a physically smaller inductor at the lower value.
4. Consider using a 16V BP cap C1056 since this 4.7uF cap will derate quite significantly with 5V bias.
5. I see ramp resistor R1166 is not populated which corresponds to a ramp capacitor of 29.1pF. Did they determine this setting through lab evaluation on an EVM or another way?
6. Add a resistor in series with top feedback network as an injection resistor for bode plot measurements:
   
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