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LM5116: Minimizing SW node ringing by using gate resistor

Shane Buckham
Prodigy 70 points
Part Number: LM5116
Other Parts Discussed in Thread: LM5146, , PMP11257, LM5146-Q1

Hi,

I am concerned about SW node ringing when the high side MOSFET turns on. My Vin is 87V (abs max) but I want to use 100VDS MOSFETs if it all possible. I therefore need to carefully ensure there is very limited SW node ringing.

One approach to this as identified in the datasheet is to use a gate resistor up to 2.2R to slow down the high side MOSFET drive. In comparison however the LM5146 datasheet which has an almost identical topology suggests placing the same 2.2R in series with the boost capacitor. This second option seems better to me as is slows down turn on but not turn off, this seems a more power efficient approach. Can you advise?

Also if you can please explain how the gate driver can experience negative voltages as per the LM5116 datasheet version SNVS499H:
"In some applications it may be desirable to slow down the high-side MOSFET turnon time in order to control switching spikes. This may be accomplished by adding a resistor is series with the HO output to the high-side gate. Values greater than 10 Ω should be avoided so as not to interfere with the adaptive gate drive. Use of an HB resistor for this function should be carefully evaluated so as not cause potentially harmful negative voltage to the high-side driver, and is generally limited to 2.2-Ω maximum"
Interestingly a TI reference design PMP11257 uses a 10R resistor which would seem to not adhere to the above datasheet recommendation.

Many Thanks,

Shane

  • 0
    TI__Guru 73952 points

    Hi Shane,

    The best way to mitigate ringing is to optimize the PCB layout by minimizing the area of the input cap - MOSFET switching loop. Minimizing the parasitic inductance of the switching loop is critical as the stored energy in the parasitics resonates and ultimately dissipates during the switching transition. For power stage layout best practices, see app note snva803. Also, see part 6 of "The engineer's guide to EMI in DC-DC converters" on how2power.com.

    In terms of gate resistance, you are correct - placing it in series with the boot cap means only the turn-on transition is affected. The amount of gate resistance depends on the Ciss of the FET and other FET parameters. The gate loop inductance is also critical as this results in oscillatory gate waveforms, hence the recommendation to route HO and SW as a diff-pair from the controller to the high-side FET. See the PCB layout guidelines in the LM5146-Q1 datasheet for more detail.

    Regards,

    Tim

    www.ti.com/widevin

  • 0 in reply to Timothy Hegarty
    Prodigy 70 points

    Hi Tim,

    All very useful and those are great articles.

    I'm trying to stick with 2 layer PCB if possible due to cost so I am planning to slow down the high side turn on speed and allow for a snubber in addition to your golden principles around minimizing parasitics.

    I get that the gate resistor is very dependent on the selected MOSFET with the goal to not interfere with the adaptive gate drive, however slowing down the turn on only would not seem to be at risk of causing any issue there. My main impact would be increased switching losses. Do you agree?

    Can you provide any clarification on the datasheet comment regarding the negative voltage on the gate driver "... so as not cause potentially harmful negative voltage to the high-side driver" ? I'm missing something but I cannot see what mechanism causes this negative voltage in relation to gate resistor.

    Many Thanks,

    Shane

     

  • 0 in reply to Shane Buckham
    TI__Guru 73952 points

    Hi Shane,

    Yes, correct, the main impact of the gate resistance is an increase in switching losses.

    Negative voltage on the gate at turn off is related to gate loop parasitic inductance, and the gate voltage may resonate below GND (or SW for the high side). Typically, there are internal diodes from GND to LO and LO to VCC (or SW to HO and HO to BST) related on the MOS pullup and pulldown devices, but these diodes typically do not limit the high-frequency spikes. 

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 70 points

    Hi Tim,

    I assume the external low side MOS intrinsic diode will not do much to help this negative voltage at high frequency either?

    Thanks,

    Shane

  • 0 in reply to Shane Buckham
    TI__Guru 73952 points

    Hi Shane,

    The duration of ringing is typically too short for the body diode to turn on and clamp. Moreover, the resonance is also sustained across the package bond wire and external circuit parasitic inductances.

    Regards,

    Tim

    www.ti.com/widevin

  • 0 in reply to Timothy Hegarty
    Prodigy 70 points

    HI Tim,

    OK, understand. Many thanks for your expert advise!