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TPS23756: Behavior when CS exceeds VCSMAX

Michael Balourdas
Expert 5455 points
Part Number: TPS23756

Hello,

In section 7.3.4 of the datasheet, it states "The current limit threshold, VCSMAX, defines the voltage on CS above which the GATE ON time will be terminated regardless of the voltage on CTL." However, looking at the Functional Block Diagram of section 7.2, it appears that having a signal on the CS pin which exceeds VCSMAX (~0.55V) would set the internal flip-flop's CLRB low which then sets the GATE output high, regardless of the voltage on CTL. Can you clarify which is correct?

Thanks,

Michael

  • 0
    TI__Mastermind 21320 points

    Hello Michael,

    Thanks for your question, it is a good one. 

    I am confirming with our team, but if the flip flop's CLRB pin is active low, meaning if a LOW is put on CLRB it clears the flip flow and forces the output low, then that would be consistent with the rest of the datasheet. If not, then it looks like a further investigation is in order. 

    Let me get back with you once I have a confirmation. Thank you!

  • 0 in reply to Michael Pahl
    TI__Expert 5455 points

    Hi Michael,

    Any luck here?

    Thanks,

    Michael

  • 0 in reply to Michael Balourdas
    TI__Mastermind 21320 points

    Michael,

    Not yet but I will let you know. 

    If this post answers your question, please indicate so by marking this thread as resolved. Thank you.

     

    Regards, 

     

    Michael P.

    Applications Engineer

    Texas Instruments 

  • 0 in reply to Michael Pahl
    TI__Mastermind 21320 points

    Hello Michael,

    So I confirmed with our team the the CLRB pin is active LOW since the B stands for Bar. That would result in the CS pin  > 0.55V give a high, then the OR-NOT gives a LOW, which give a LOW for CLRB which means the Flip Flops clears the output and forces it low which forces the AND gate and the pin GATE low. 

    This is consistent with the verbiage in the datasheet. Thank you!

    If this post answers your question, please indicate so by marking this thread as resolved. Thank you.

     

    Regards, 

     

    Michael P.

    Applications Engineer

    Texas Instruments 

  • 0 in reply to Michael Pahl
    TI__Expert 5455 points

    Hi Michael,

    That makes sense, thanks for clearing that up!

    Very similar question: The datasheet also says that VCTL < VZDC (1.5V) will force GATE low. If I follow the BD, it looks like a VCTL below VZDC will force the first comparator high, and assuming VCS < .55, forces the NOR gate high which gives a HIGH for CLRB which keeps GATE on.

    Is my understanding correct or did I mess up somewhere? 

    Thanks,

    Michael

  • 0 in reply to Michael Balourdas
    TI__Mastermind 21320 points

    Hello Michael,

    I understand what you are saying; I made the table below for the OR-NOT gate and how it relates to the CTL, CS and GATE pins. I put this before our System's engineer who helped write the datasheet. He should be the one who can either clarify the answer or confirm if there is a datasheet error. 

    Input A (NOT)

    Input B

    Output (NOT)

    CTL > Vzdc

    CS < 0.55

    GATE = Forced to LOW

    CTL > Vzdc

    CS > 0.55

    GATE = Forced to LOW

    CTL < Vzdc

    CS < 0.55

    GATE = can be switching

    CTL < Vzdc

    CS > 0.55

    GATE = Forced to LOW

    I would expect the part has IF CT: > Vzdc and CS < 0.55 then the GATE is free to be switching. Otherwise one or both of these conditions would shut it off. However when I follow the logic, that is not the result I find. 

    The good news is this part has been on the market for years and behaves as described in words in the datasheet.  We can arrange to send you or your customer an EVM if we need a proof of concept. My guess is there is either something we are not understanding or there is a datasheet error. I have encountered both, but I won't say which one occurs more often..

    I'll let you know when I do!

    If this post answers your question, please indicate so by marking this thread as resolved. Thank you.

     

    Regards, 

     

    Michael P.

    Applications Engineer

    Texas Instruments 

  • 0 in reply to Michael Pahl
    TI__Expert 5455 points

    HI Michael,

    Thank you, please let me know once you find out where the mix up is.

    Regards,

    Michael

  • 0 in reply to Michael Balourdas
    TI__Mastermind 21320 points

    Hello Michael,

    So we are having to climb the escalation chain from systems to design. I will send follow up email.

    Regards,

    Michael Pahl