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TPS546D24AEVM: input current at full load

MINKYUNG KIM
Expert 1250 points
Part Number: TPS546D24AEVM

Hi there,

Could you kindly explain the test conditions as the attachment below? As far as I understand about the buck, input current is the sum of output current and IC-operating current, in that, input current is similar to or slightly larger than output current. So input current should be around 80A at full load condition in this 2PH EVM I expect from my understanding, but what the test condition presents is that the input current is typically 6.4A and 15.6A in full load (Iout = 80A). Please help my understanding. Thank you!

  • 0
    TI__Guru 52485 points

     

    The input current of a BUCK regulator averaged over 1 switching cycle is eff x (VOUT / VIN) x IOUT, and the input capacitors on the EVM design will average the individual cycle by cycle pulses of current, so the input current specification is for the averaged input current, not the dynamic currents within a switching cycle.

    Yes, this is drawn in very small pulses of current equal to 80A when the Control, or high-side FET is on, but it needs to be averaged with the 0A input current periods when the high-side FET is off and the output current is flowing through the rectifying or low-side FET.

    For an 80A output at 0.8V, the total output power is 64 Watts, so the total input current will be slightly higher than 64W / Vin.

    For the "typical" case (Vin = 12V) 64W / 12V = 5.33A, the 6.4A spec allows for an efficiency of 83%

    For the low VIN case (Vin = 5V) 64W / 5V = 12.8A, the 15.6A spec allows for an efficiency of 82%

  • 0
    TI__Guru 52485 points

     

    Since the TPS546D24EVM is a 2-phase design, the peak input current into each phase is only half of the load current, or 40A when the total output current is 80A.  This doesn't change the other details I provided, but high-lights that in the multi-phase design, the peak currents are reduced, even at the average currents remain the same.

    The duty-cycle of the individual phases remains at VOUT/VIN to maintain the VOUT voltage, but with 2 such pulses per switching cycle, only half of the average output current is drawn from the input with each control FET on-time.

  • 0 in reply to Peter James Miller
    Expert 1250 points

    Things are very clear. Thank you so much!