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TPS51200: Compliance to JEDEC DDR3 standards

Part Number: TPS51200
Other Parts Discussed in Thread: TMS320C6678

Hi TI team:

I'm using TPS51200 to power DDR3 sections for my TI DSP (TMS320C6678) and 4 SDRAMs (from Samsung - K4B2G1646F-BMMA).

(1) As per JEDEC standard for SDRAMs (JESD79-3F), the dc-tolerance limits for VRefCA and VRefDQ, indicated [VRef(DC)max and VRef(DC)min] is given by ±1% VDD (i.e., ± 15mV; VDD = 1.5V). The datasheet of TPS51200 tells that if VREFIN = 0.75V (ideally, with 1% resistor tolerances), then VREFOUTTOL (REFOUT voltage tolerance to VREFIN) = ± 12mV.

If 12mV is the dc-tolerance of REFOUT rail, does that mean that while designing PCB, the worst case IR drop allowed on the board level is only: 15mV – 12mV = 3mV?

 

(2) As per JEDEC standard for SDRAMs (JESD79-3F), the ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than ±1% VDD (for reference: approx. ± 15 mV).

How much of ac noise is introduced by TPS51200 at the REFOUT pin?

 

Thanks and Regards,

Binayak

  • Hi Binayak, 

    TPS51200 REFOUT is LDO output. The REFOUT (VREF) current from DIMM is very small (a few uA for each DIMM) and also this current is a DC current.

    Therefore the IR drop and the ripple on REFOUT is very small.

    Thanks

    Qian

     

  • Hi Qian:

    From your reply, what I'm believing is that if I place the regulator close to the 4 SDRAMs, and then provide a wide power trace/plane to connect the REFOUT pins from the regulator to VRefCA and VRefDQ pins of the SDRAMs, and provide the decaps as recommended by the SDRAM manufacturer, then powering of VREF pins of the DDR3 sdrams through TPS51200 should be ok.

    Am I correct?

    Thanks,

    Binayak

  • Hi Binayak, 

    The Refout (Vref) current from each DRAM is only a few uA, the I*R drop on the trace can be ignored. 

    A regular signal trace is enough. No need to use wide power trace/plane for the connection. 

    Thanks

    Qian