Sunny,
We don't have reference design of ISO5852S driving parallel SiC (2 FETs driven by each driver), however this can be done. In the case that ISO5852S can't provide sufficient drive current for the parallel case, an external buffer (push-pull) can be used to increase drive strength. Or, UCC217xx family can be used which has higher drive current .
For your second question, if you are asking on how to determine with the 'short circuit' detection DESAT protection threshold, keep in mind it is voltage based and not exactly current based. DESAT detects "desaturation" of the FET which isn't as effective on SiC. Essentially it detects VDS/VCE increasing out of the saturation region. As far as what IDS current this occurs at, it would depend on that device IDS/VDS curve at the drive voltage. This might be available in the FET datasheet.
The threshold for DESAT detection can be calculated in the datasheet here.
If OC (series resistor) based detection is required, UCC217xx family might be better option than ISO5852S.
If you are instead asking how to find out if a certain configuration ( gate resistor + FET) will exceed the drive current rating of ISO5852S, there is a simple way to estimate shown in the below Technote.
Technote on IOH/IOL currents
In the equations below, the highlighted values should be changed to the Peak/max values for ISO5852S from the datasheet. Thermal also should be calculated. Could be under the peak drive current limits but still exceeding temperature
Please let me know if you have any further questions.
Best
Dimitri
