Other Parts Discussed in Thread: LM3409
I'm using the LM3409-Q1 as shown in www.ti.com/lit/zip/dlpr059
When power is removed from the system the FPGA detects this based on it's own UVLO circuit. When this happens the FPGA should drive the LED_EN to the LM3409-Q1 low. For the FPGA this should happen when VBAT = 9.5V and the UVLO for the LM3409-Q1 should trip at 9.9V.
Based on the above what I would expect to see on a scope capture is that the LED_EN signal would go low when the FPGA UVLO happens. However what I'm seeing is that the LED_EN signal goes low when the LM3409-Q1 UVLO is triggered. Is there something internal to the LM3409-Q1 that would cause the EN pin to be pulled low during UVLO?
