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Original question:

TPS2596: TPS2596 Simulation files

TPS2596: TPS259621

Steve Green
Intellectual 430 points
Part Number: TPS2596

I downloaded the TPS259621 file and ran the following sim using values from the spreadsheet. The UVLO should be 4v but I am only getting 1.5 in the sim. I changed the values to force UVLO to 5v, but device still did not turn on. is there a problem in the model or am I just missing something?

 i want to use this device since the item I'm working on is Hot Swap. The 9v source is a keep alive battery for when its unplugged.power fail 3.TSC

File attached

  • 0
    TI__Guru 57737 points

    Hi Steve,

    There is a resistor divide connected to the UVLO pin (R6 = 1Mohm and R7 = 430k). When the input voltage is 5V, the resistor divider steps down the voltage at UVLO to 1.5V. If you change the resistor divider circuit, the voltage at UVLO pin is changing acordingly. So, I dont see a problem with the UVLO pin functionality.

    The problem I see is that the DVDT capacitor is set to 47uF. This will allow very very small inrush current into the device and hence the efuse will take a very long time to startup. You can change the DVDT cap to a lower value say 10nF or 22nF and run the simulation. You will see that the device starts up successfully. Please use the design calculator available in the below link to design your efuse circuit.

    https://www.ti.com/product/TPS2596#design-development

  • 0 in reply to Praveen GD
    Intellectual 430 points

    Hi Praveen,

    Thanks for the reply, You're right, the UVLO should be 1.5v. had a senior moment. The 47u was a typo on my part, the spreadsheet came up with 47nf. When I used the 47nf the sim would not converge. Anything larger than 18nf doesn't converge. Any ideas?

    Steve

  • 0 in reply to Steve Green
    Intellectual 430 points

    Hi Praveen,

    Another quick question. The data sheet says the FLT is only active for overtemp and ILM short. In the sim, the FLT is low with power removed. I assume this is because the FLT output is pulled up to an active voltage (system powered by backup) and the body diode of the FET is turned on. There is no current spec on this. The pullup in the micro is 20k min. Would it be safe to use this as a power fail flag? If so, I can eliminate the extra comparator i have. The Backup is controlled by the micro, I am just using the comparator output in the sim.

    Thanks,

    Steve

  • 0 in reply to Steve Green
    TI__Guru 57737 points

    Hi Steve,

    Can you try simulating in PSPice ? 

    Yes, FLT/ is only asserted when the internal FET is turned OFF due to Overtemperature, Overvoltage or ILM Pin Short to GND.

    FLT/  is an open drain output pin and needs to be pulled up externally. The pullup resistor selected must ensure that the current sunk by FLT/ pin should not exceed 10 mA. PLease refer to section 9.2.4 is datasheet.

    If the FLT/ is pulled up to an external power supply, it can be pulled high even when the device is not powered.