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LM5069: Startup oscillation, current spikes causing circuit breaker tripping?

David Gomez1
Prodigy 100 points
Part Number: LM5069
Other Parts Discussed in Thread: TPS2663

Hello, 

I have a design with an LM5069 that is displaying an abnormal looking oscillatory behavior on the startup along with multiple current spikes. 

The design includes a diode and extra NFET to enable reverse voltage protection - the design is based off of one I found in this app note: SLVUAA1

I have attached:

- Relevant schematics 

- PCB layout image

- Design Calculator values 

- Some scope captures 

 

Please note that I have made some changes to the PCBs I am testing:

- R202 = 1.58k

- R203 = 6.65k

- D400A = replaced with 7.5k resistor 

- D401A = DNP

- R406 = 7.5k

- In the real application, the net "36V_STEP" connects to an additional PCB with ~2000uF of capacitance through a long wire, HOWEVER, I see this issue with and with and without this PCB connected though. All of the scope captures are taken without this extra capacitance. 

"capture_1.png" shows the issue:

- Yellow: IN_OUT, FET source

- Green: IN_GATE, GET gate

- Blue: Input current, (measured with RT-ZC15B current clamp around wires going into PCB)

In the beginning, we see the current rise and then stabilize at the power limiting current level. Eventually though, we see a large spike in current and oscillatory behavior on the gate drive. I believe then the circuit breaker is tripped, and the gate is pulled down. After this we see the gate voltage increase and then we continually see this current spike until we reach a point where the voltage is able to reach its final level of 36v.  

"capture_2.png" shows:

- Yellow: IN_OUT, FET source

- Green: IN_GATE, GET gate

- Orange: 36V_STEP, output voltage

- Blue: Input current, (measured with RT-ZC15B current clamp around wires going into PCB)

On theory I had was that my power limit was too low creating instabilities due to unexpected loads during turn on or issues with the sense resistor voltage being read. I initially calculated the circuit values based on the datasheet, however, when I redid them in the calculator I realized I had a large amount of margin for the FET SOA. I used a 49.9k resistor to give an ~50W power limit. With this I see that the circuit breaking behavior occurs thorough-out the entire startup sequence, this is no normal looking section in the beginning as seen before. 

"capture_3.png" shows:

- Yellow: IN_OUT, FET source

- Green: IN_GATE, GET gate

- Blue: Input current, (measured with RT-ZC15B current clamp around wires going into PCB)

In application note SNVA683 I noticed that they removed capacitor 0.1uF C5 which in my circuit is C203. I removed this capacitor. I see that the current spike was much larger. There are fewer oscillations but I think that is only because the output was charged to the point where the oscillations stop anyway. 

My current theory is that there is an issue with the control loop in my circuit. It seems like it could be one of two things:

1. the current to gate voltage response is too slow, the current starts increasing but gate voltage cannot respond before the circuit breaker is tripped

2. the control loop is unstable and there is positive feedback causing the current to runaway until the breaker trips

Do you have any thoughts on what could be the cause of this issue based on this information? I can take more measurements as needed. If the control loop theory seems reasonable, what might be the issues causing it in the circuit? 

Thanks,

David

TI E2E LM5069.zip

  • 0
    TI__Guru** 105361 points

    Hi David,

    Thanks for reaching out!.

    What is the application and end product ? If you are early in the design phase, TPS2663 would be a good option to simplify your solution.

    Coming to the LM5069 issue...

    1. With lower power limit setting, the circuit is timing out and attempting multiple restarts

    2. When power limit is increased, the controller tries to source more current to the load which triggers fast-trip due to heavy capacitive load.

    To solve this, please use dvdt startup in Step-d of the design sheet and check. I have attached modified design sheet for reference.

    Please also refer app note: http://www.ti.com/lit/an/slva673a/slva673a.pdf

    copy_LM5069_Design_Calculator_REV_C_David.xlsx

    Best Regards, Rakesh

  • 0 in reply to Rakesh
    Prodigy 100 points

    Hi Rakesh,

    Thanks for the info, the end application is for a stepper motor controller for a robotic system. TPS2663 does look interesting and it is not out of the question to switch to it if the LM5069 proves impossible, I will look into it more to see how much it simplifies the solution. The only things I am really looking for out of this solution is reverse voltage protection, inrush protection for large capacitive load (nominally 2,890uF, large electrolytics have +/-20% tolerance though), low Rdson. The current limiting is nice, however, for this application we may not want it to be very hard, as in a small 7A transient shouldn't shut the system down. 

    With regards to the LM5069:

    1. Please note on this design I am currently using the LM5069-1 with the latching fault. I don't think the circuit is timing out because it is able to start up successfully and then the system operates normally. From my understanding, if the LM5069-1 timed out during a startup, the output voltage would never reach its final level and the input power would have to be cycled in order attempt a restart. 

    2. With the power limit increased, I am still questioning why the current appears so "spiky". Even with 50W, at the initial Vds of 36V, we should be seeing a current of ~0.7A which should then start increasing as Vds decreases until the current limit of ~6A is reached at which point the constant 6A current should be maintained until the capacitors are fully charged. I am expecting a much more continuous current ramp from the graphs I have seen in the datasheet and app notes, it seems as though the LM5069 is not able to regulate the current to a constant level.   

    I can look into the dv/dt startup; however, my understanding from the videos in the calculator was this is should only need to be used in situations where it is impossible to stay within the FET SOA with the normal power limits/timer capacitors. The current design stays well within the FET SOA even with the 50W limit. Is the dv/dt startup then also useful in a situation like this where it appears current is rising too quickly for the LM5069 to respond?

    Thanks,

    David

  • 0 in reply to David Gomez1
    TI__Guru** 105361 points

    Hi David,

    I think, I overlooked on the current spikes. Correct, the regulation loop is going out of control after a while. One reason I could think of is due to lack of individual GATE resistors for each FET. This can cause oscillations under regulation mode of operation in multi-FET configuration especially with high gm FETs. Please refer https://toshiba.semicon-storage.com/info/docget.jsp?did=59458 

    Can you please check the behavior under below two conditions.

    1. with 10Ohm in series of each MOSFET GATE. 
    2. Remove Q201 and short the path.

    Best Regards, Rakesh

  • 0 in reply to Rakesh
    Prodigy 100 points

    Hi Rakesh, 

    Thanks for the suggestion and the app note. I added a 10ohm resistor between the gate of the first NFET Q200 and the GATE pin of the LM5069. 

    I am now seeing a much more stable and continuous current (blue) rise exactly as expected. The rise of Vgs (cyan) is much more stable and is not showing the oscillatory behavior from before. 

    Thank you very much!

    David

  • 0 in reply to David Gomez1
    TI__Guru** 105361 points

    Hi David,

    You are welcome! But please consider adding dv/dt startup circuit as it has large output capacitance. 

    You also mentioned the output goes and connects to an additional PCB with ~2000uF of capacitance. If it is a hot-plug connection, consider inrush protection on that additional PCB before 2000uF cap.

    Best Regards, Rakesh