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TPS650864: Power sequence for ZU7EV

na na78
Guru 16770 points
Part Number: TPS650864
Other Parts Discussed in Thread: TPSM846C24

Hi

I'm considering power sequence for ZU7EV.

I drew a sequence diagram for every power rails.

7658.e2e.xlsx

Could you please check this sequence?  And is it feasible for the TPS650864?

BestRegards

  • 0
    TI__Genius 17380 points

    Hello,

    This looks like the TPS6508640 OTP settings. It looks to me like you already used the TPS6508640 OTP Generator file to make this, but if not it is located here: www.ti.com/.../swcc027

    Comments:

    1. Might be worth noting that the BUCK2_PG signal is reflected on the GPO1 pin (vs all the other PG signals are internal only)
    2. BUCK1 requires BUCK2_PG AND CTL4 pin high. Usually CTL4 pin is connected to VCCINT_PG but you could short GPO1 to CTL4
    3. SWA1 is enabled by BUCK5_PG
    4. LDOA1 is enabled by BUCK6_PG
    5. Probably don't need to list CTL3 as part of the VTT enable, CTL3 is the main sequence enable so it is redundant to include it again. I mean to say that every rail would include an "& CTL3" or "& CTL3 & CTL4" but I think it is clear that is implied by the sequence.
    6. Is current on Rail F really 4.6A? The maximum current estimate we received from Xilinx for this rail was 1.4 A.

  • 0 in reply to Kevin LaRosa
    Guru 16770 points

    Hi Kevin

    Thank you for your reply.

    I attached the flow chart with some update.

    2804.e2e_v2.xlsx

    Yes, I'm referring TPS6508640 OTP settings and drew this sequences.
    I'd like to work with default settings of TPS6508640.

    >Might be worth noting that the BUCK2_PG signal is reflected on the GPO1 pin (vs all the other PG signals are internal only)
    I think the GPO1 is assigned as BUCK2_PG signal, So it would be asserted if BUCK2 out is well regulated.
    I plan to use it for external DCDC enable.
    Of course, I'm sure that BUCK2_PG is used for internal register too (for an enable of BUCK1).
    If I'm having a misunderstanding, please tell me.

    >BUCK1 requires BUCK2_PG AND CTL4 pin high. Usually CTL4 pin is connected to VCCINT_PG but you could short GPO1 to CTL4
    Thank you for your notify. The flow chart was not correct.
    CTL4 is connected to VCCINT_PG of the external DCDC (Rail A').

    >SWA1 is enabled by BUCK5_PG
    Yes. SWA1 would be enabled after BUCK5. I modified flow chart.

    >LDOA1 is enabled by BUCK6_PG
    Yes. But CTL1 should be asserted too, shouldn't it?

    >Probably don't need to list CTL3 as part of the VTT enable, CTL3 is the main sequence enable so it is redundant to include it again.
    >I mean to say that every rail would include an "& CTL3" or "& CTL3 & CTL4" but I think it is clear that is implied by the sequence.
    Yes. I understand.

    >Is current on Rail F really 4.6A? The maximum current estimate we received from Xilinx for this rail was 1.4 A.
    Is that true? Our estimation of Rail F(MGTAVTT, VCC_PSPLL) would be around 4.6A.
    Only MGTAVTT is 4.46A. We used Xilinx Power Estimator (XPE) for ZU7EV.

    So, I had mistake in the flow chart. (BUCK3 could not supply over 3A)
    I will change BUCK3 for Rail F to ext DCDC which is enabled by BUCK4_PG (GPO4).

    However, I'm interested in what you are telling.
    If MGTAVTT should be lower than 1.4A, BUCK3 can be used. That should be better!


    BestRegards

  • 0 in reply to na na78
    TI__Genius 17380 points

    Hi,

    I just want to confirm that you have looked at the sequence in Figure 6-4 of the datasheet that shows the power up sequence? 

    Your redrawing is getting closer to matching the existing drawing but still has a few gaps. For example, LDOA1 is shown from SWA1 but should be from BUCK6.

    You also included CTL1 for LDOA1 but not for BUCK6; CTL5 is missing from VTT LDO. 

    As far as MGTAVTT, I incorrectly listed 1.4A, that was for a ZU5EV, not ZU7EV. For ZU7EV, the value provided by Xilinx to us was 2.1 A. However, the data was from 2017 and I don't know if they included every possible use case. It may be that this is a special use case with much higher current. My suggestion is to double check if it is configured correctly but I do not mean to question the result. You are correct that if they need that much power, the BUCK3 cannot support it. Please note that the BUCK3 feedback will still need 1.2V applied to it during the proper sequence in order to not power fault and cause the PMIC to shutdown.

  • 0 in reply to Kevin LaRosa
    Guru 16770 points

    Hi Kevin

    Thank you for your reply.

    >I just want to confirm that you have looked at the sequence in Figure 6-4 of the datasheet that shows the power up sequence? 

    Yes.  

    As you say,  my drawing was not precise.  I modified it a little.

    e2e_v3.xlsx

    And as you pointed out, I have forgotten that BUCK3 should be regulated even if it is not in use.  I will take care of it.

    Regarding CTLx pins, 

    CTL1 and CTL3 is connected together
    CTL2 is connected to '0' (gnd)
    CTL4 is connected to VCCINT_PG from TPSM846C24
    CTL5 is connected to LDO3P3
    CTL6 is connected to '0' (gnd)

    If you have any concern, I appreciate if you feedback to me.

    BestRegards

  • 0 in reply to na na78
    TI__Genius 17380 points

    No more feedback from me currently. Let us know if there are any additional questions.

  • 0 in reply to Kevin LaRosa
    Guru 16770 points

    Hi Kevin

    Thank you for your cooperation.  We will move forward development.

    BestRegards