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TPS65910's nRESPWON and PWRHOLD relationship

Jiansheng Liu
Intellectual 310 points
Other Parts Discussed in Thread: TPS65910

I want to understand the timing relationship between nRESPWRON and PWRHOLD two signals on TPS65910. From the boot mode timing relation shown page 31 (Figure 3 Boot mode 01) it is indicated that nRESPWRON is released to HIGH after PWRHOLD, during this period each of power rails are turn on in sequence. It makes sense to me since we want to release the reset only after all of power rails are up. However the figure 4 in next page shows PWRON turn-on/off process gives different process: PWRHOLD signal will be hold additional TdONPWHOLD time AFTER nRESPWON has been release to HIGH. It conflicts with the description in last page. 

Can some help to explain what is the correct timing relation here? About  nRESPWRON and PWRHOLD, which one will be released first?

 

thanks

Jiansheng 

  • 0
    TI__Genius 15100 points

    Hi,

    In the first diagram, PWRHOLD is used as a enabled event and hence you see that as the first signal that starts the power-on sequence. This is generally the case when another device is master and wakes up TPS65910 using the PWRHOLD pin.

    In the next diagram the device ON and OFF events are based on the main voltage inputs. As given in the notes in the same diagram there is a requirement for PWRHOLD to be high to keep all supplies ON. If you refer to the user guides for this PMIC you will notice that PWRHOLD is tied high to satisfy this requirement. 

    Because the two power up conditions are different you see the signals in a different sequence.

    Hope this helps.

     

    Regards,

    Gandhar.