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TPS544C25: more information about FSM

Cedrick
Expert 8270 points
Part Number: TPS544C25

Hi, 

Good day. I hope everything is fine. 

Our customer is undertaking a component assessment of some of our devices. They need some clarification, please, to assess the suitability of the TPS544C25. The datasheet talks about the FSM hitting non or multiple states.  They want to clarify if this FSM is used for controlling the PMBus interface or if it is controlling the core functionality, and any further details you can on the FSM please?

I hope you could provide more information about this. 

Thank you and have a great day. 


Regards,
Cedrick

  • 0
    TI__Guru 56825 points

     

    The FSM is the Finite State Machine.  It is a fixed frequency, clocked digital logic core that handles the digital logic functions within the TPS544C25.  I handles all of the PMBus Processing, start-up, DAC slew-rate control, shut-down and fault response handling.  The STATUS_MFR_SPECIFIC fault bits - Illegal Zeros and Too Many Ones specifically refers to the operational state finite stage machine.

    The single hot states referred to in the STATUS_MFR_SPECIFIC bits include Disabled, Ton Delay, Soft-Start, Regulating, Toff Delay, Soft-Stop, Fault, Hiccup, Latch-off to track the operational state of the converter and control its response to control pin and various analog fault detection circuits.