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UCD3138: UCD3138 About ACOMP setting

user5952333
Intellectual 280 points
Part Number: UCD3138

Hello.

 

We are currently confirming the operation using UCD3138.

 

The detection voltage is connected to the port of the analog comparator B, and the FIQ interrupt is set when the overvoltage is detected.

This time, with the detection voltage connected to the analog comparator, the interrupt setting for voltage detection was stopped and it was running. As a result, a log was recorded that was recorded only by the FIQ interrupt for overvoltage detection, even though the overvoltage did not occur.

The voltage detection interrupt settings are as follows. Is it possible that an interrupt will occur with this setting?

Also, the value of the FAULTMUXINTSTAT register recorded when the interrupt occurred was 0x00000000. Is a FIQ interrupt of FAULT_INT generated in this state?

If so, what should I consider the interrupt factor?

 

【The interrupt setting for voltage detection ACOMP_B】

FaultMuxRegs ACOMPCTRL0 ACOMP_EN = 1

 

FaultMuxRegs ACOMPCTRL0　ACOMP_B_THRESH　= 0 (default)

FaultMuxRegs ACOMPCTRL0 ACOMP_B_SEL = 0 (default)

FaultMuxRegs ACOMPCTRL0 ACOMP_B_POL = 0 (default)

 

FaultMuxRegs ACOMPCTRL0 ACOMP_B_INT_EN = 0 (default)

 

FaultMuxRegs DPWM0FLTABDET ACOMP_B_EN = 0 (default)

FaultMuxRegs DPWM1FLTABDET ACOMP_B_EN = 0 (default)

FaultMuxRegs DPWM2FLTABDET ACOMP_B_EN = 0 (default)

FaultMuxRegs DPWM3FLTABDET ACOMP_B_EN = 0 (default)

 

Dpwm0Regs DPWMFLTCTRL ALL_FAULT_EN = 1

Dpwm1Regs DPWMFLTCTRL ALL_FAULT_EN = 1

Dpwm2Regs DPWMFLTCTRL ALL_FAULT_EN = 1

Dpwm3Regs DPWMFLTCTRL ALL_FAULT_EN = 1

 

CimRegs FIRQPR = 0x0A000000

CimRegs REQMASK = 0x0A020000

 

 

Best Regards.


  • 0
    TI__Genius 17090 points

    If you don't have the interrupt enable bit set, you should not get the interrupt.  If the FAULTMUXINTSTAT bit is not set, you should not see the IRQ register bit set for the fault mux interrupt in the Central interrupt modult.  Something doesn't add up in what you are saying. .  

    Reconstructed code with o's instead of zeroes may have be incorrect, or you may be setting bits somewhere else.

    It's also possible that you have some other fault enabled to interrupt, and that this is causing the bit in the IRQ register to be set.  

  • 0 in reply to Ian Bower
    Intellectual 280 points

     

    The CimRegs register setting is 0 (zero) , not O.

       CimRegs FIRQPR = 0x0A000000

       CimRegs REQMASK = 0x0A020000

     

    There are nowhere settings for CimRegs register except above.

     

    However, the FAULT INT interrupt is actually occurring. (FAULTMUXINTSTAT bit not set)

     

    What should I suspect?

  • 0 in reply to user5952333
    TI__Genius 17090 points

    I still suspect your conclusion that you get a fast interrupt from the fault mux at the same time as none of FAULTMUXINTSTAT bits are being set.  

    The FAULTMUXINTSTAT bits are clear on read, so you may be clearing them after you receive the interrupt.  After you read the FAULTMUXINTSTAT register, please check the fault interrupt bit in the INTREQ register to see if it is set.  

  • 0 in reply to Ian Bower
    TI__Genius 17090 points

    It's been a week since my last answer.  I'll assume that you have solved the issue, maybe with my help, so I'm going to try to close this thread.