TPS53211: Dead time of TPS53211

Hi,

It's a very old part. I even can't the EVM on TI.com. It's a controller, not a buck converter. My understanding is that the dead time is determined by the controller's sourcing and sinking current capability and the external MOSFET's  Cgs. Without the certain external MOSFET, we might not know the real dead time. If you have the TPS53211 and board on hands, I suggest you to do some test with your selected MOSFET.

user6168601 

This is Peter James Miller, senior applications and customer support engineer with Texas Instruments and the applications lead for the TPS53211 controller.  The TPS53211 controller uses an adaptive Break-before-Make dead-time control architecture that monitors the Vgs voltages at the pins (LGATE to GND for the low-side FET and UGATE to PHASE for the high-side FET) to control the dead-time between the two FETs.  This allows the controller to adapt the dead-times for external FET conditions, gate capacitance, temperature variations, etc while maintaining the smallest amount of time between the turn-off of one FET and the turn-on of the other.

The High-side to Low-side dead time is measured from UGATE to PHASE dropping below 1V to the start of the rise of LGATE above GND, and typically measures 15ns, though it can be as high as 30ns.

The Low-side to High-side dead time is measured from the LGATE to GND dropping below 1V to the start of the rise of UGATE above PHASE, and typically measures 15ns, though it can be as high as 25ns.

Measuring the dead-time at other voltages, such as the 90% falling to 10% rising, delay will produce longer delays that do not represent the body diode conduction or anti-cross-conduction periods, and are heavily influenced by external factors, such as FET gate charge and switch node transition rate.

Because the anti-cross conduction circuitry works by sensing the UGATE to PHASE and LGATE to GND voltages, adding series gate drive resistors will reduce the actual dead-time as the LGATE and UGATE voltages are able to transition faster than the FET's actual gate voltage.  This is generally not an issue when small resistances are used with moderate gate charge FETs, but using a large gate drive resistor along with a large gate charge FET can result in gate voltages that are significantly delayed and force cross-conduction.  Due to the higher gate charge typically used on lower Rdson low-side FETs, they is most common for the UGATE falling LGATE rising dead-time.