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TPS3838-Q1: Spurious reset

Part Number: TPS3838-Q1
Other Parts Discussed in Thread: TPS3838

We are using the TPS3838K33QDBVRQ1 in our design.

On some modules, the device generates a reset, while we cannot see the cause of the reset.

The 3V3 power supply does not fall below 3.15V and the MR input is stable at 3.15V.

The marking on the device is: PDVQ

I cannot find this marking in the datasheet. Is it the correct device?

Thanks,

Mark.

  • Hi Mark,

    That is the correct part marking for that device, it is listed at the end of the datasheet in the orderable devices section. On how many units is the issue seen?

    Thanks,
    Abhinav.

  • Hi Abhinav,

    Thanks for your fast reply. The only marking I can find in the datasheet is the PDVI, not the PDVQ.

    I have seen this issue on 2 units out of app 150 units.

    The time between errors is approximately a few days, so it is quite hard to capture.

    At the customer site, the modules are normally not operational for more than one day, so there may be more modules in the field with this issue that we are not aware off.

    Is it possible that the device generates a reset pulse on a spike-event on either the power supply or the MR input?

    What is the minimum time for the VDD and MR pin to be below the threshold voltage to be detected?

    I am measuring at the MR and VDD pins of the device to try to capture the cause of the reset.

    Regards, Mark

     

  • Hi Abhinav,

    I have measured some spikes on the 3V3 power supply down to 2.72V.

    However, no reset was generated, at least within 15 usec (limited to the memory of the oscilloscope)

    I will improve the power supply.

    For my interest:

    The datasheet specifies the propogation delay time of VDD to RESET:

    VIL = VIT - 0.2V, VIH = VIL+0.2V : 10 usec.

    VIL = 1.6V : 50 usec.

    I do not fully understand this specification.

    Does the TPS3838 generate a RESET on a spike of the power supply? 

    Can you please clarify this specification?

    Thanks,

    Mark

  • Mark,

    Apologies for the delay in response. The propagation time is the time to which RESET asserts after it has met the VDD condition.

    Thanks,
    Abhinav.