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UCC28950: I would like to ask about Lmag design values.

Lewis Kevin
Intellectual 500 points
Part Number: UCC28950
Other Parts Discussed in Thread: UCC28951

Hello,

I'd like to ask some question as follows since I have faced some problem when I am designing a 5kW converter using UCC28950.
Lmag cannot be achieved due to the limited winding space of the transformer.
According to the excel document provided, it states more than 0.9mH. but when we wind it actually, 500uH is the maximum.

When designed with a 500uH transformer, the magnetizing current will increase as the Lmag decreases.
Therefore, we will design the Rcs resistor in order that the value input to the CS pin is less than maximum 2V .
If you have any considerations other than this one, please kindly advise me.

There are many information for CCM type, but I couldn't find a design guide for VCM.
Is it only necessary to connect the Rsum resistor to the Vref?

I assume that other parts (for example, Voltage Loop Compensation) seems to change the design..
so if you have any data on this, would appreciate for sharing with me as well.

Looking forward to hearing from you soon.
Thank you in advance.

  • 0
    TI__Mastermind 25570 points

    Hello Su-min

    There is not very much information about VMC because the vast majority of applications for this device use current mode control. If you want to run the device in VMC (and despite what I just said - there are some applications where VMC is used successfully) then simply use a resistor to connect the RSUM pin to VREF. The UCC28950 uses an internal ramp when it is in Voltage control mode. The value of RSUM should be chosen in the usual way to set the amount of slope compensation used during a current overload (CS signal reaches the 2V limit) when the Cycle-by-Cycle comparator operates to terminate the switching cycle. Slope compensation is not needed for Voltage mode control of course but the controller is effectively operating in current control mode during a current overload.

    In Voltage mode control you will also need a DC blocking capacitor in the primary of the power transformer.

    The loop compensation does change in VMC because the control to output transfer function is very different. There are some details in https://www.ti.com/seclit/ml/slup340/slup340.pdf and https://www.ti.com/seclit/ml/slup113/slup113.pdf?ts=1591349464896

    and http://www.ti.com/lit/an/slua119/slua119.pdf?ts=1591349558851 and http://www.ti.com/lit/an/slva301/slva301.pdf?ts=1591349574936

    note that the PSFB (UCC28950) is a buck derived topology so the equations for the buck converter in the above apply - modified to take account of the the transformer turns ratio -

    Regards

    Colin

  • 0 in reply to Colin Gillmor
    Intellectual 500 points

    Hello Colin.

    First of all, thank you for your kind reply.
    I have one more question.
    If the Lmag value of Transformer is about one-half the capacity of the design, what kind of trouble makes? And the CS voltage value may be set below 2V, is it impossible to control CMC?

    Thank you for your help.

  • 0 in reply to Lewis Kevin
    TI__Mastermind 25570 points

    Hello Su-min

    If you use voltage mode control then having a lower value of Lmag won't be a problem.

    If you use peak current mode control (PCM) then -----

    In PCM the system compares the CS signal to the output of the error amplifier (COMP pin in the UCC28951). The CS signal is usually derived from the input current to the H bridge - (as in the 'Typical Application Schematic') and this signal is a composite of the output inductor current + the magnetizing current of the transformer and a slope compensation ramp is usually added too. What we want to control is the current in the output inductor. Let's assume that the magnetizing current is zero (infinite Lmag) then the CS signal accurately represents the output inductor current. As Lmag reduces the magnetizing current increases and the output inductor current is not represented as accurately. Eventually the magnetizing current dominates the CS signal and the current in the output inductor becomes only a small fraction of the total CS. So, what happens as Lmag reduces is that the system changes from a pure PCM system where the output inductor current is controlled accurately to a system which behaves increasingly as if it were operating in Voltage mode. This is a bit of a simplification because I have ignored the need for a slope compensation ramp.

    In practice, if the slope of the magnetizing current is less than 50% of the downslope of the output inductor current (reflected through the transformer turns ratio of course) then the magnetizing current acts as part of slope compensation ramp - and may provide enough slope compensation to eliminate the need for any additional ramp. This is the condition used in the data sheet to set the minimum Lmag for PCM.

    If Lmag is half the limit set in the DS than the system should still behave as if it were in PCM -

    If Lmag is less than half the limit then you should model the system and make sure you can get the loop bandwidth you need.

    In the UCC28951 the peak CS signal at which the controller enters Cycle-by-Cycle current limiting is 2V at the CbC comparator.

    So - that's a qualitative explanation - a fully quantitative explanation is at 

    http://www.ridleyengineering.com/images/current_mode_book/CurrentModeControl.pdf page 198 et seq

    and some additional information about slope compensation is at https://www.ti.com/seclit/ml/slup113/slup113.pdf?ts=1591609651505&ref_url=http://www.ti.com/ww/en/power-training/login.shtml

    Note that there is some debate about whether the optimum slope compensation ramp is 50% or 100% of the inductor current downslope - different authors use different criteria for 'optimum'. Given the tolerances involved I'd tend to go for the middle ground here and use 75%

    Please let me know if you need any more information.

    Regards

    Colin

  • 0 in reply to Colin Gillmor
    Intellectual 500 points

    Thank you so much for the professional and detailed explanation.
    When modeling using Matlab, the phase margin is secured
    In design, I will apply that both VMC and PCM can be set, and may select one of them later after enough tests.

    If I face problems again that cannot be solved, we may ask for your advices again
    Thanks again for your kind replies!

    Have a great day!

  • 0 in reply to Lewis Kevin
    TI__Mastermind 25570 points

    Hello Su-min

    I'm glad I was of some help - please feel free to contact us again if you have any questions. I'm going to close this thread now - you can always open a new thread.

    Regards

    Colin