Hi,
I'm now playing with the TSP23730EVM-093. I'm trying to verify functionality of the PPD pin. I would like to use this IC in a daisy-chained PoE application, where voltage can drop even below 30V due to resistive losses on the line.
The datasheet claims that "Raising VPPD-VSS above 2.5 V enables the hotswap MOSFET, activates TPH and TPL and turn class off." However, I'm not observing this behavior on the EVM. Output load (DC-DC converter) is always turned on/off around 35V (Vdd-Vss) regardless of PPD setting (tied to VSS or to certain voltage from the divider).
In particular, I measured following:
PPD configuration | voltage when load was turned on Vdd-Vss |
voltage when load was turned off Vdd-Vss |
PPD tied to VSS (J5 left open) | 35.7V | 35.4V |
J5 shorted, 100k-15k default divider | 35.6V | 35.5V |
J5 shorted, 100k-22k divider | not turned on in order to protect PDD from exceeding 6V |
not turned on in order to protect PDD from exceeding 6V |
J5 shorted, 100k-11k divider | 35.7V | 35.5V |
Note 1: With the 100k-15k and with the 100k-11k dividers the TPL and TPH went low according to the datasheet (diodes D7 and D8 turned on). So it somehow detected voltage present on the PPD pin and pushed TPL and TPH low but did not adjust the UVLO accordingly.
Note 2: With the 100k-22k divider, voltage on the PPD pin approached 6V when Vdd-Vss was around 33V. I would probably approach abs max rating of this pin very closely if I would approach turn-on/off voltage of 35V. So I rather did not further increase the voltage.
For sure, the load is not turned on/off around 2,5V on the PPD pin.
Am I doing something wrong? Could you provide me your explanation, please?
One more important observation. The PPD pin shall not experience voltage larger than 6.5V. However, with the 100k-15k divider on the EVM and with the upper voltage threshold of 57V it can experience even 7.4V! I understand that it is designed for lower voltage, but then you should not claim "42-57V" at the J3 connector (see schematic).
Best regards,
Jan.