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TPS65381A-Q1: Meaning of NRES_ERR - When will it be set?

Stephan HERMANNS
Intellectual 590 points
Part Number: TPS65381A-Q1

Dear Team of PMIC support,

I'm not sure why a state transition ACTIVE -> SAFE instead of a transition ACTIVE -> RESET should occur, if (WD_FAIL_CNT=7+1 & WD_RST_EN=1) and (NRES_ERR=1).

Assuming the PMIC is in state ACTIVE and the watchdog tries to set NRES = 1 but NRES keeps 0 instead due to any random fault.
According to figure 6 in the TPS65381's datasheet from my point of view in this case there are two possible state transitions:
(T1) ACTIVE -> SAFE as NRES_ERR=1, provided DIS_NRES_MON=0 // Priority III
(T2) ACTIVE -> RESET as (WD_FAIL_CNT=7+1 & WD_RST_EN=1) // Global Reset Condition , Priority II.

But as T2 is of higher priority than T1 in this case T1 would not happen.

So my question is, in which cases transition T1 is taken?
Maybe the answer is already given by figure 5-14 in which NRES_ERR is driven in two cases covered by the XOR gate and not just the case called in section 5.5.4.5.

Thank you in advance for your support

Stephan

  • 0
    TI__Expert 4690 points

    Hi Stephan,

    I am not sure I follow the concern. 

    Below are some comments:

    • In case (WD_FAIL_CNT=7+1 & WD_RST_EN=1) occurs, this will cause a Global RESET condition with Priority II. This means that the device will transition to RESET state regardless of the current state (the only exception is if the device is in STANDBY state).
    • An ACTIVE->SAFE transition will occur as long as no Priority II event occurs AND (ERROR_PIN_FAIL=1 OR [NRES_ERR=1 AND DIS_NRES_MON=0]) occurs.

    If this does not clarifies your concern could you please reference the correct figure in the statement below (figure 6 is not an actual figure in the datasheet)

    Stephan HERMANNS said:
    According to figure 6 in the TPS65381's datasheet from my point of view in this case there are two possible state transitions:

    Regards,
    Ivan 

  • 0 in reply to Ivan Calzada
    Intellectual 590 points

    Good morning, Ivan,

    Sorry for my mistake, the correct reference is figure 5-16, not figure 6.

    I understand the higher priority of the global reset condition compared to a priority II transition.

    But how about the deviation between figure 5-14 and section 5.5.4.5?

     

    As i understand figure 5-14, the case (pin=high, control=low) called in section 5.5.4.5 is only one of two cases covered by the xor gate in figure 5-14.
    The other would (pin=low, control=high). In this case the priority II transition to SAFE state would be taken but the transition to RESET state due to the global reset condition would not, right?

    Best wishes

    Stephan

  • 0 in reply to Stephan HERMANNS
    TI__Expert 4690 points

    Hi Stephan, 

    Thank you for your clarification. I am reviewing your observation with Systems and will try to get back to you by with additional clarification by Friday.

    Regards,
    Ivan 

  • 0 in reply to Stephan HERMANNS
    TI__Expert 4690 points

    Hi Stephan,

    Although in theory NRES_ERR could be set to 1 due to two scenarios you have already identified:

    • Scenario 1: (NRES pin output HIGH and NRES pin input readback LOW) and
    • Scenario 2: (NRES pin output LOW  and NRES pin input readback HIGH)

    Only under "Scenario 1" the application could be able to read NRES_ERR status and the device's state machine would only be able to react to this fault if the device is in ACTIVE state and DIS_RES_MON = 0.

    In order for "Scenario 2" to occur, NRES pin need to be LOW. Which means that either the device is either on STANDBY or RESET state. As shown in Figure 5-16 of the datasheet, the device could be on STANDBY or RESET state due normal state transitions or due to a PRIORITY I or II. Therefore, a transition to SAFE should not occur under Scenario 2 (Please note that all transitions to SAFE state are PRIORITY III). 

    Best regards,
    Ivan