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UCC21222: bootstrap cap configuration

Lenio Cacula
Genius 16700 points
Part Number: UCC21222

My customer has issues with charging up the bootstrap cap in the circuit attached. I ran simulations achieving somewhat similar results, also attached. The top curve is the voltage across the bootstrap cap C15 - it never charges. The simulation starts at VDDA, but the real circuit starts at zero and remains zero. What is wrong with the configuration of the circuit?

UC21222 simulation v2.pdf

Results v2.pdf

  • 0
    TI__Expert 3355 points

    Hi Lenio,

    Taking a quick look at your schematic, it looks like D3 would clamp VSSA to VDDAIN which would hinder the switch node from rising > VDDAIN. What was the intent behind this diode? I suggest removing D3 and retesting.

    Secondly, if that doesn't work, I recommend looking at D4 and making sure it has proper voltage rating and low reverse recovery. If it is too low voltage rating, it will avalanche and prevent proper operation of the bootstrap circuit. If it has high reverse recovery, it is possible for a lot of charge to be lost before it fully recovers, resulting in similar looking waveforms.

    If this helped, can you please press the green button?

    Thanks,

    John

  • 0 in reply to John Geiger
    TI__Genius 16700 points

    John,

    thanks for the prompt reply!

    I simulated the circuit without D3 and with an ideal diode at D4 - the results are the same.

    Do you have other ideas? Evidently these new results could be a circumstance of the simulation. If you feel strongly about that, I can ask the customer to do the same in the real circuit.

    Thank you!

  • 0 in reply to Lenio Cacula
    TI__Expert 3355 points

    Hi Lenio,

    I also see that signals going to INA and INB seem to go high at the same time. There should ideally be a time delay between these two signals, or else the gate driver will try to turn on both outputs at the same time, causing shoot through. Typical half-bridge inputs are complementary. I also recommend adding a resistor >1kOhm from DT (pin 6) to GND in order to enable overlap protection and prevent shoot through.

    You can actually see that the apparent switch node is only going between 0 to ~35V, instead of the 0 to 100V expected.

    I might recommend lowering V7 to 0V as well, just to ensure nothing weird is happening with bit precision of the absolute voltage - though I do not think that is happening here.

    If you are still having trouble after fixing the input signals, can you please share your sim file here?

    Thanks,

    John

  • 0 in reply to John Geiger
    TI__Genius 16700 points

    John,

    the input signals came from UCC21222 PSpice model we have in our product page. It works well and you can see that the signals are complementary (180°). I agree we could see shoot-through since the deadtime is little (10ns rise and fall time of the pulses).

    The model is attached. Thanks for the help!Export_UCC21222_sim.zip

  • 0 in reply to Lenio Cacula
    TI__Guru**** 189401 points

    Hi, Lenio,

    Let us check this out and get back to you with our findings.