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UCD3138: About the errata of UCD3138

user6369729
Prodigy 85 points
Part Number: UCD3138

I don't know the workaround for the following errata described in 2.5 of "UCD3138 Integrated Power Controller Family Errata" issued by TI.

Please tell me how to set the register specifically.

https://www.ti.com/lit/er/sluz033a/sluz033a.pdf?ts=1592438114461&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCD3138

Best regard,

  • 0
    TI__Mastermind 18370 points

    Hi,

    What is your exact part number?

    If it is UCD3138(without A), please set:

    Dpwm0Regs.DPWMSAMPTRIG1.bit.SAMPLE_TRIGGER = 5;

    as in the TI's LLC EVM.

    Regards,

  • 0 in reply to Yitzhak Bolurian
    Prodigy 85 points

    Hi, Yitzhak 

    Thanks for the comment.

    The part number is UCD3138 (without A).

    Sorry,I didn't know what LLC EVM was.

    I use the UCD3138 for phase shift control of DC-DC converters.

    Errata 2.4 describes the LLC converter. Does this mean I don't have to worry about this errata unless it's an LLC converter?

  • 0 in reply to Yitzhak Bolurian
    Prodigy 85 points

    Hello! Yitzhak

    It is an additional question.

    I'm using the following sample firmware.

    -> "Design & development"

       -> "Software development"

          -> "UCD3138 Phase Shift Full Bridge Firmware"

    If I use this sample firmware as is, can I avoid Errata 2.4?

    If not, please tell me the correction contents to avoid errata 2.4.

    Best Regards,

  • 0 in reply to user6369729
    TI__Mastermind 18370 points

    Yes.

    The comment is addressing an issue with LLC topology.

    Please ignore this if you are not implementing LLC.

    Regards,

  • 0 in reply to user6369729
    TI__Mastermind 18370 points

    Errata 2.4 is specifically referring to LLC.

    But as a general rule the sample trigger should be positioned 500 nS before the end of period in any application.

    In UCD the propagation delay from the time the EADC samples the output voltage till the digital filter (PID) provides output to the DPWM (or to the inner current loop in case of PCM) is about 450 nS. That is why we recommend that the sample trigger to be positioned at 500 nS before the end of period, so the fresh PID output will be ready before the update required.

    Regards,