ISO5852S: Questions about BJT circuit and the STO

Lena, thanks for your questions.

Lenna Yan said:

1. Why choose 10Ohm resistor between OUTH/OUTL and base of BJT? How to judge the resistor value used here?

That resistor value is determined by BJT base current required by the designer, which itself could be back-calculated from the BJT collector current and current gain from the datasheet. This of course is the final drive current to the power switch IIGBT/FET.

In a lot of designs they are exactly the same value, or even a single resistor is used, because the Power BJTs are sold by the manufacturers as "complementary pairs" with the same or similar performance for pull-down and pull up, but that isn't always necessarily the case to use "complementary pairs" of bjts.

Lenna Yan said:

2. In the datasheet, it indicates the STO procedure disable OUTH and pull OUTL to low over a time span of 2us. 

What are the factors that will terminate the 130mA internal STO current source during the soft turn off procedure? For example the Vge discharged to VEE2, the soft turn off time is over 2us?

Thats a great question! And honestly the timing diagrams and explanations in the datasheet don't explain it well. That 2us figure is not going to be the same for every IGBT or FET. it would depend on the gate charge/gate cap.

Below, is the process for Soft-turn off (note that the 150ns for glitch filter should be replaced with the 330ns from the datasheet)

Essentially, the process is as follows:

After the glitch timer for DESAT satisfied,

* OUTPUT is disabled

* STO current begins discharging gate by the specified STO current

* Once the gate voltage is reduced down  to the Miller clamp threshold (2.1V referenced to VEE2), STO current ends, and Miller clamp and OUTL both pull the gate down.

So the STO current will stop once gate reaches 2.1V above VEE2, at which point, the miller clamp and OUTL will both pull the gate down the rest of the way to VEE2.

So, the end-time of STO current is based on when the gate reaches the Miller clamp threshold, and will depend on the gate charge of the FET or IGBT in the customers system. The timing figures reports t_desat10% at a specific capacitive load.

I hope this answers your questions. Let me know if you have any further questions!

I've attached some caps from the datsheet and highlighted the relevant timing.

Lenna,

Lenna Yan said:

Hi James,

Thanks so much for your reply. I have one more question. Is the 330ns glitch filter time a part of the desat sense to 10% output delay?

Glitch filter time is not considered part of  that delay figure because DESAT is not sensed until the glitch filter time has been fulfilled.

Best

Dimitri