Do we have any guidance on the error amplifier offset voltage and input bias currents? These are needed for worst-case analysis.
If the worst case offset is included within the Vref spec - that would be sufficient. There is a figure 10 in the current datasheet that mentions offset vs the SS pin - that seems pretty high @ 10mV-30mV over temperature - Is that the offset referred to Vfb as well?
For the input bias current - we mention in section 7.3.3 that there is a Vsense input current and that the divider resistors should not be too high in value to minimize the impact of that current but we don't provide a max value - do we have any guidance for this?