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TPS25942A: The number of vias

Michiaki Tanii
Expert 4610 points
Part Number: TPS25942A

Hi team,

 

In the layout example, there are six vias but customer designed layout and they can place only two vias due to via size.

Are there any concern if the board is placed only 2 vias ?

And also please let me know how to determine the number of vias.

 

Thank you and best regards,

Michiaki

  • 0
    TI__Guru 57737 points

    Hi Michiaki,

    Are you referring to the via's placed on the signal ground plane ? 

    This PowerPAD must be connected to a PCB ground plane using multiple vias for good thermal performance. Having more via's to connect the top layer ground plane to the bottom layer ground plane helps in transferring heat to the bottom layer. 

    There is no fixed number of vias that you need to have on your board. It is just that more the number of vias on your gnd plane more the heat transfer to the bottom layer and better the RQJA of the IC. If you have only 2 vias, it means that the RQJA of the IC degrades a little. 

    Try to maximize the number of vias and the GND plane area to improve RQJA of the IC. 

  • 0 in reply to Praveen GD
    TI__Expert 4610 points

    Hello Praveen,

     

    Customer will use φ0.4 for vias.

     

    Could you kindly advise the number of vias customer should place ?

    And if customer has only 2 vias, how much will RQJa regrades ?

     

    Thank you and best regards,

    Michiaki

  • 0 in reply to Michiaki Tanii
    TI__Guru 57737 points

    Hi Michiaki,

    It is very difficult to estimate the RQJA with the information of No. of Vias as it depends on many parameters like Copper Thickness, Copper plane area, Air Flow/Cooling in the system etc.. The reliable way to estimate the RQJA is to measure it after the boards are built (for a known power loss in the device how much is the temperature rise ?). 

    For your reference we have RQJA value mentioned in the datasheet which is measured on a standard JEDEC board.

    As mentioned, the only thing you can do is to try to maximize the number of vias and the GND plane area as much as possible to improve RQJA of the IC.